PARALLEL BUS ARBITRATION Search Results

F8H SMD

Abstract: DIP20 HVQFN20 JESD22-A114 JESD22-A115 JESD78 PCA9564 PCA9665 SO20
Contextual Info: PCA9665 Fm+ parallel bus to I2C-bus controller Rev. 03 — 12 August 2008 Product data sheet 1. General description The PCA9665 serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus

74HC12

Abstract: ST-BUS MH89760B MH89790B MT8920B MT8920BE MT8920BP MT8920BS MT8976 MT8979
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8920B ST-BUS Parallel Access Circuit  Features • • • • • • • • ISSUE 7 High speed parallel access to the serial ST-BUS Parallel bus optimized for 68000 µP mode 1 Fast dual-port RAM access (mode 2) Access time: 120 nsec

stpa

Abstract: MH89760B MT8920B MT8920BC MT8920BE MT8920BP MT8920BS MT8976 MT8979 tx-1c
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8920B ST-BUS Parallel Access Circuit  Features • • • • • • • • ISSUE 6 High speed parallel access to the serial ST-BUS Parallel bus optimized for 68000 µP mode 1 Fast dual-port RAM access (mode 2) Access time: 120 nsec

M82C284

Contextual Info: intei M82289 BUS ARBITER FOR M80286 PROCESSOR FAMILY Military Supports Multi-Master System Bus Arbitration Protocol Three Modes of Bus Release Operation for Flexible System Configuration Synchronizes M80286 Processor with Multi-Master Bus Supports Parallel, Serial, and Rotating

Contextual Info: 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

Contextual Info: In te l 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device -Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

MC68HC11PH8

Abstract: HC11 MC68HC711PH8 a41dc Nippon capacitors CON34
Contextual Info: MC68HC11PH8/D MC68HC11PH8 HC11 TECHNICAL DATA MC68HC11PH8 MC68HC711PH8 TECHNICAL DATA !MOTOROLA !MOTOROLA INTRODUCTION 1 PIN DESCRIPTIONS 2 OPERATING MODES AND ON-CHIP MEMORY 3 PARALLEL INPUT/OUTPUT 4 SERIAL COMMUNICATIONS INTERFACE 5 MOTOROLA INTERCONNECT BUS MI BUS

PCA9665

Abstract: JESD22-A114 JESD22-A115 JESD78 PCA9564 PCA9665D PCA9665N PCF8584
Contextual Info: NXP Fast-mode Plus parallel bus to I2C-bus controller PCA9665 1-MHz I2C-bus control on longer buses This is the first master device to be compatible with Fast-mode Plus, so it offers ten times the speed or ten times the capacitance as standard Fast-mode masters. It can communicate at I2Cbus speeds up to 1 MHz and on buses up to 4,000 pF.

TS68230CP8

Abstract: PLCC52 TS68000 TS68230 68440
Contextual Info: TS68230 HMOS PARALLEL INTERFACE/TIMER . . . . . TS68000 BUS COMPATIBLE PORT MODES INCLUDE : BIT I/O UNIDIRECTIONAL 8 BIT AND 16 BIT BIDIRECTIONAL 8 BIT AND 16 BIT PROGRAMMABLE HANDSHAKING OPTIONS 24-BIT PROGRAMMABLE TIMER MODES FIVE SEPARATE INTERRUPT VECTORS

82C389

Contextual Info: V LSI Technology, in c VM82C389 MESSAGE-PASSING COPROCESSOR MULTIBUS II FEATURES DESCRIPTION • Full-function, single-chip interface to Parallel System Bus PSB The VM82C389 Message-Passing Coprocessor (MPC) provides a highintegration interface solution for the

JESD22-A114

Abstract: JESD22-A115 JESD78 PCA9698 PCA9698BS PCA9698DGG TSSOP56 78 DIODE SMD
Contextual Info: PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Rev. 02 — 19 July 2006 Product data sheet 1. General description The PCA9698 provides 40-bit parallel input/output I/O port expansion for I2C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable

HI-6121

Contextual Info: HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface SPI MIL-STD-1553 Remote Terminal ICs GENERAL DESCRIPTION “RoHS compliant” lead-free option is offered. REMOTE TERMINAL FEATURES • Fully integrated 3.3V Remote Terminal meets all

PCA9698BS

Abstract: PCA9698DGG JESD22-A114 JESD22-A115 JESD78 PCA9698 TSSOP56 TSSOP56 package
Contextual Info: PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Rev. 3 — 3 August 2010 Product data sheet 1. General description The PCA9698 provides 40-bit parallel input/output I/O port expansion for I2C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable

Contextual Info: 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • • Two Instructions/Clock Sustained Execution Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET PRODUCT PREVIEW DESCRIPTION • Bit-serial SDH/SONET line interface - Pseudo-ECL interface with clock recovery and synthesis • Byte-parallel SDH/SONET line interface

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

Contextual Info: in te l SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining i • 32-bit Parallel Architecture

4N15

Abstract: 1038 0E1 txc-06103arbg
Contextual Info: PHAST-3N Device STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET TXC-06103-MB, Ed. 8 December 2007 FEATURES APPLICATIONS • Byte-parallel SDH/SONET line interface, parity detection/generation with optional frame pulse input

Contextual Info: Intel 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • ■ ■ High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

16C550

Abstract: 82077AA NS16C550 PC99 HP-95 GP22 LAD T2
Contextual Info: LPC47B37x 100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications FEATURES • • • • • • • • • • • • • • • • • 3.3 Volt Operation 5V Tolerant Floppy Disk Controller (Supports 2 FDCs) Multi-Mode Parallel Port

Contextual Info: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 TECHNICAL OVERVIEW • • • • • • • • • • • • • • • • Byte-parallel SDH/SONET line interface - Parity detection/generation with optional frame pulse input

HI-6121

Abstract: hi6121
Contextual Info: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a

Contextual Info: i. |-v.? I ? ÿ-'H í í iC- i.- i, í ? í -i ;: XR16C872 r 'VV í Dual UART with 1284 Parallel Port and Plug-and-Play Controller X *E X d R June 1999-1 FEATURES • IrDA Infrared Pulse Shaping Encoder/Decoder for up to 115.2Kbps Data Rate • Plug and Play ISA Bus Specification Compliant