000243B Search Results

fuse code Jd 0,7A

Abstract: odv marking PM5323 PM5344 PM5361 PM5371 TU12
Contextual Info: S tan d a r d PM I / I P roduct _ _ _ PRELIMINARY INFORMATION P M C -S ie rra , Inc. PM5361 TUPP SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FEA TU R ES • Configurable, multi-channel, payload processor for alignment of SONET virtual tributaries VTs or SDH tributary units (TUs). Processes an STS-3 or STM-1 byte

50E30

Contextual Info: Preliminary IM P 50E 30 EPAC Programmable Monitoring and Diagnostic 1C Electrically Programmable Analog Circuit Introduction The IM P5 0 E3 0 is a programmable IC offering a variety o f m onitoring, diagnos­ tic and data-acquisition capabilities. Its operating modes increase system

486 motherboard schematic

Abstract: 486dx2 pinouts 486DX2 486dx schematic 4021-A TL05A Super386 t187 T106B J7 CHIPS TECHNOLOGIES
Contextual Info: CHIPS & TECHNOLOGIES INC SIE D • SO Töllb DDOSSba 4ÖT M C H P 9000-380 8 CHIPS CHIPS & TECHNOLOGIES INC S1E » ■ EQTflllb □□□PPbM 31S MCHP T -v 1 -1 7 -0 1 Copyright Notice Software Copyright 1992, Chips and Technologies, Inc. Manual Copyright © 1992, Chips and Technologies, Inc.

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Abstract: RZ26L RZ26 dec 21040 tty00 DKA400 eb64 BA 6688 L pc motherboard schematics Alpha 21064
Contextual Info: Alpha Microprocessors Motherboard Debug Monitor User’s Guide Order Number: EC–QHUVF–TE Revision/Update Information: This is a revised document. It supersedes the Alpha Microprocessors Motherboard Debug Monitor User’s Guide, EC–QHUVE–TE. Digital Equipment Corporation

Contextual Info: IBM11M2720Q 2M x 72 D R A M M O D U LE Features • System Performance Benefits: • 168 Pin JEDEC Standard, 8 Byte Dual In-line Memory Module - • 2Mx72 Dual Bank Fast Page Mode DIMM • Performance: -60 -70 Buffered inputs except RAS, Data Reduced Noise (32 Vss/Vcc pins)

Contextual Info: GaAs MMIC SPDT Reflective Switch Dual Positive Control DC-2500 MHz EBAlpha AS373-12 Features • Low Loss <0.5 dB @ 900 MHz ■ Dual Positive Control Logic ■ Positive Voltage Operation (+3 to +5V) ■ Low DC Power Consumption ■ Extremely Low Cost ■

Contextual Info: S ta n d a rd P r o d u c t PM I I PMC-Sierra, Inc. / PREUMINARY INFORMATION PM5361 TUPP SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FEA TU RES • Configurable, multi-channel, payload processor for alignment of SONET virtual tributaries VTs or SDH tributary units (TUs). Processes an STS-3 or STM-1 byte

Contextual Info: 5SE D • 3213074 000243S 2 ■ _ T-25-31 Peak switching SSR • • • • • • • AC solid state relay. Peak switching for transformers. 10,25, and 50 A load current. Up to 1200 Vp non-repetltlve voltage. Up to 480 VnMS line voltage. Input range; 4-32 VDC.

Contextual Info: IIIIICRTRLYST / • V II P relim inary S E M I C O N D U C T O R CAT28F102 1 Megabit CMOS Flash Memory FEATURES ■ Fast Read Access Time: 90/120/150 ns 64K x 16 Word Organization ■ Low Power CMOS Dissipation: -Active: 30 mA max CMOS/TTL levels -Standby: 1 mA max (TTL levels)

Contextual Info: 3 2 K x 8 mosaic SRAM MSM832-55/70/85/10 Issue 4.2 : JUNE 1996 semiconductor, inc. 32,768 x 8 CMOS High Speed Static RAM Description Features The MSM832 is a high speed Static RAM organ­ ised as 32K x 8 available with access times of 5 5 ,7 0 ,8 5 or 100 ns. The device is available in