00133M Search Results

TRU050-TACGA

Abstract: TRU050
Contextual Info: Data Sheet TRU050 Clock Recovery and Data Retiming Module Features • Quartz crystal stabilized by internal VCXO ■ User-defined loop filter for tailoring performance ■ Input data and clock rates from 50 kHz to 52 MHz ■ NRZ data compatible ■ Low transition density capability

Contextual Info: ADVANCE MT4LC4M16N3/R6 4 MEG X 16 DRAM l^ iic n g N 4 M E G X 16 D R A M S DRAM 3.3V, EDO PAGE MODE PIN ASSIGNMENT Top View • Single +3.3V +0.3V power supply • Industry-standard x l6 pinout, timing, functions and package • 13 row-addresses, 9 column-addresses (N3) or

of mq2

Contextual Info: Panasonic Others DN8646FBP 4 X 8 -bit Shift Register Latch Driver 1C • Overview The DN 8646FB P is an 1C which incorporates a 4 x 8-bit shift register and a latch driver to m eet high-speed opera­ tion, low power consumption and high-density printout of

Contextual Info: CMOS 8-Bit Single-Chip Microcomputers LC 867000 Series under development Overview The LC867000 Series CMOS 8-bit single-chip microcon­ trollers are high-speed, advanced-function microcomputers with on-chip LCD controller/drivers, 8-bit A/D converters, and

qml-38535

Abstract: HCTS30 S962X
Contextual Info: REVISIONS LTR DATE YR-MO-DA DESCRIPTION APPROVED t REV SHEET REV SHEET 15 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REV SHEET 1 2 3

Contextual Info: Panasonic Others DN8643S 24-bit Shift Register Latch Driver 1C • Overview The DN8643S is an 1C which incorporates a 24-bit shift register and a latch driver to meet high-speed operation, low power consumption and high-density printout of the thermal printers for the work processors, and so on. It

Contextual Info: 24FC32 M icrochip 32K 5.0V 1 MHz CMOS Serial EEPROM FEATURES PACKAGE TYPE • Voltage operating range: 4.5V to 5.5V - Maximum write current 3 mA at 5.5V - Maximum read current 150 jiA at 5.5V - Standby current 1 |iA typical • 1 MHz SE2.bus two wire protocol

LT1220

Contextual Info: u im Q M M , Final Electrical Specifications LTC1410 TECHNOLOGY 12-Bit, 1.25Msps S am p ling A /D C o n v e rte r w ith S hutd o w n April 1995 F€nTUft€S D e s c n iP T io n • Complete 1.25Msps ADC ■ Power Dissipation: 160mW Typ ■ Nap (7mW) and Sleep (1 OpW) Shutdown Modes

Contextual Info: |U |IC R O N MT4C16270 256KX 16 DRAM 2 5 6 K x 16 DRAM DRAM 5V, EDO PAGE MODE • Industry-standard x l6 pinouts, tim ing, functions and packages • High-performance CM O S silicon-gate process • Single +5V +10% pow er supply* • Low power, 3m W standby; 300m W active, typical