0071C Search Results

Agere read channel

Abstract: DATA Sheet IC 555 84 PLCC pin configuration data sheet book ic 555 Ringing Subscriber Line Interface Circuit NXP T8533 T8534 T8535B T8536B T8538B
Contextual Info: Preliminary Data Sheet September 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Contextual Info: T8535B/T8536B Quad Programmable Codec Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5 V operation Per-channel programmable gains, equalization, termination impedance, and hybrid balance Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

T8533

Abstract: T8534 T8535B T8536B T8538B
Contextual Info: Data Sheet March 2002 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Contextual Info: SIEMENS PEB 20320 Functional Description 2 Functional Description 2.1 Serial Interface The serial interface of MUNICH32 includes a data receive RDATA and a data transmit line (TDATA) as well as the accompanying control signals (RCLK = Receive Clock, RSP = Receive Synchronization Pulse, TCLK = Transmit Clock, TSP = Transmit

44256 dram

Abstract: reclaimer intel date code format 28F800B3 AT29C432 GF105 GM99
Contextual Info: D Flash Data Integrator FDI User’s Guide July, 1997 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

Contextual Info: Features • ■ ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame — Supports PCM data rates of 512 kbits/s to 16.384 Mbits/s — Double-clock mode timing compatible with ISDN

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT ¿¿PD75P316A 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The /¿PD75P316A is a product of the /iPD75316 with on-chip ROM having been replaced with the one-time PROM or EPROM . It is most suitable for test production during system development and for production in sm all amounts since it