1 OF 8 ADDRESS LATCH Search Results

P8085AH

Abstract: TMP8085AP TMP8085AP-2 TMP8085 TMP8156P MPU85-9
Contextual Info: TO SHIBA TMP8085A TMP8085AP-2/TMP8085AHP-2 8-BIT MICROPROCESSOR 1. GENERAL DESCRIPTION The TMP8085AP-2/TMP8085AHP-2, hereafter on referred to as TMP8085A, is a 8 bit micro processing unit MPU . TMP8085A uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The on-chip address latches of

Contextual Info: PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143C – OCTOBER 2006 – REVISED JUNE 2007 FEATURES • • • • 1-of-8 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Address by Three Hardware Address Pins for

pd548a

Contextual Info: PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143C – OCTOBER 2006 – REVISED JUNE 2007 FEATURES • • • • 1-of-8 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Address by Three Hardware Address Pins for

PD548A

Contextual Info: PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143C – OCTOBER 2006 – REVISED JUNE 2007 FEATURES • • • • 1-of-8 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Address by Three Hardware Address Pins for

sc413

Abstract: A115-A C101 PCA9548A PCA9548ADBR PCA9548ARGER sc516
Contextual Info: PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143C – OCTOBER 2006 – REVISED JUNE 2007 FEATURES • • • • 1-of-8 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Address by Three Hardware Address Pins for

Contextual Info: PCA9548A 8-CHANNEL SWITCH WITH RESET I2C www.ti.com SCPS143C – OCTOBER 2006 – REVISED JUNE 2007 FEATURES • • • • 1-of-8 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Address by Three Hardware Address Pins for

Hitachi DSA00279

Contextual Info: HD74HC356 8-to-1-line Data Selectors/Multiplexer/Register with 3-state outputs Description This data selectors/multiplexers contain full on-chip binary decoding to select one of eight data sources. The data select address is stored in transparent latches that are enabled by a low level address

D5N diode

Abstract: Hitachi DSA002789
Contextual Info: HD74HC354 8-to-1-line Data Selectors/Multiplexer Register with 3-state outputs Description This data selectors/multiplexers contains full on-chip binary decoding to select one of eight data sources. The data select address is stored in transparent latches that are enabled by a low level address

54FCT138

Abstract: 54FCT138DMQB 54FCT138FMQB 54FCT138LMQB E20A J16A W16A
Contextual Info: 54FCT138 1-of-8 Decoder/Demultiplexer General Description Features The FCT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three

54FCT138

Abstract: 54FCT138DMQB 54FCT138FMQB 54FCT138LMQB E20A J16A W16A
Contextual Info: 54FCT138 1-of-8 Decoder/Demultiplexer General Description Features The FCT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three

54FCT138DMQB

Contextual Info: 54FCT138 1-of-8 Decoder/Demultiplexer General Description Features The FCT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three

diode M160

Abstract: 74LVQ138 74LVQ138SC 74LVQ138SCX 74LVQ138SJ 74LVQ138SJX LVQ138 M16A
Contextual Info: LVQ138 National Semiconductor 74LVQ138 Low Voltage 1-of-8 Decoder/Demultiplexer General Description Features The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited lo r high-speed bipolar memory chip select address decoding. The multiple input enables

74LVQ138

Abstract: 74LVQ138SC 74LVQ138SJ LVQ138 M16A M16D
Contextual Info: 74LVQ138 Low Voltage 1-of-8 Decoder/Demultiplexer General Description Features The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three

74LCX138

Contextual Info: Revised December 2002 74LCX138 Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs General Description Features The LCX138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed memory chip select address decoding. The multiple input enables allow

74LCX138

Abstract: 74LCX138M 74LCX138MTC 74LCX138SJ LCX138 M16A M16D MTC16
Contextual Info: Revised February 2001 74LCX138 Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs General Description Features The LCX138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed memory chip select address decoding. The multiple input enables allow

LCX138

Abstract: 74LCX138 74LCX138M 74LCX138MTC 74LCX138MX 74LCX138SJ 74LCX138SJX SQ-57
Contextual Info: LCX138 National Semiconductor 74LCX138 Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs General Description Features The LCX138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables

LF11508

Abstract: CA 5668 mux lf11508 LF13509N MM4357 LF13508 LF13508D lf11509 LF13508N C1995
Contextual Info: LF13508 8-Channel Analog Multiplexer LF13509 4-Channel Differential Analog Multiplexer General Description The LF13508 is an 8-channel analog multiplexer which connects the output to 1 of the 8 analog inputs depending on the state of a 3-bit binary address An enable control allows

1d3e

Abstract: IC c399 D1021E
Contextual Info: BIG MEMORY 56 P1.0 / T2 / PWM0 A,source 1,2 12 Rn register addressing using R0-R7 2 1 P1.1 / T2EX / PWM1 ADD A,#data bit 8bit direct address of bit 8 10 1,2 12 rel signed 8bit offset 9 11 P1.4 / AIN1 1 24 addr11 11bit address in current 2K page 10 12 P1.5 / AIN2

IC c399

Abstract: P1217
Contextual Info: BIG MEMORY 56 P1.0 / T2 / PWM0 A,source 1,2 12 Rn register addressing using R0-R7 2 1 P1.1 / T2EX / PWM1 ADD A,#data bit 8bit direct address of bit 8 10 1,2 12 rel signed 8bit offset 9 11 P1.4 / AIN1 1 24 addr11 11bit address in current 2K page 10 12 P1.5 / AIN2

K9F1G08Q0A

Contextual Info: K9F1G08Q0A K9F1G08U0A FLASH MEMORY Document Title 128M x 8 Bit NAND Flash Memory Revision History Revision No 0.0 0.1 History Draft Date Remark 1. Initial issue 1. The tADL Address to Data Loading Time is added. - tADL Minimum 100ns (Page 11, 23~26) - tADL is the time from the WE rising edge of final address cycle

Contextual Info: 137 CO NNECTIO N DIAGRAM PINOUT A ^ 54S/74S137 D fb ^ r^ 1-0F-8 DECODER/DEMULTIPLEXER With Input Latches DESCRIPTION — The ’S137 is a very high speed 1-of-8 decoder/dem ulti­ plexer w ith latches on the three address inputs. This device essentially com ­

memorias ram

Abstract: RE53 IMS2620 IMS2620-12 Dynamic RAM Controller 673103NL 673103ANL RS52 HM256-12
Contextual Info: 1 -Megabit Dynamic RAM Control le r / Driver Features/Benefits • Supports up to 1 M DRAMs • Capable of addressing up to 8 M 16-blt words or 8 M bytes • On-chlp capacltlve-load drivers capable of driving up to 88 DRAMs with 30-nsec typical address propagation delay and

TGAM 1

Abstract: P1240A
Contextual Info: 8 0 C 1 9 6 E A C H M O S 1 6 - BI T MICROCONTROLLER Commercisi P r e l im in a r y Datasheet Product Features a 40 MHz Operation & Optional Clock Doubler 2 Mbytes of Linear Address Space 8 1 Kbyte of Register RAM 3S 3 Kbytes of Code RAM S3 Register-Register Architecture

74ALS6302

Abstract: la 7184 74ALS6301 M 6302 XP 74als630
Contextual Info: SN74ALS6301, SN74ALS6302 DYNAMIC MEMORY CONTROLLERS D 2 9 0 0 . JA N U A R Y 1 9 8 6 —REVISED M A R C H 1 9 8 8 Provides Control for 16K, 64K. 256K, and 1M Dynamic RAMs SN 74ALS6301, S N 7 4A LS 6 30 2 . . Highest-Order Two-Address Bits Select One of Four Banks of RAMs