1.9 TDI SCHEMATIC Search Results

Contextual Info: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates

THERMAL Fuse m20 tf 115 c

Abstract: SX v3.1 REQ64 A54SX08 A54SX16 A54SX32 PAR64 313 pin PBGA fq1200 THERMAL Fuse l20 tf 115 c
Contextual Info: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates

2032LV

Contextual Info: ispLSI and pLSI 2032V/LV ® 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — A IN • ispLSI OFFERS THE FOLLOWING ADDED FEATURES IM — 3.3V In-System Programmability Using Boundary

LSC 132

Contextual Info: ispLSI and pLSI 3256A ® High Density Programmable Logic • HIGH-PERFORMANCE E CMOS TECHNOLOGY — fmax = 90 MHz Maximum Operating Frequency — tpd = 12 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable

22B2 DIODE

Abstract: A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
Contextual Info: v5.2 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops

22B2 DIODE

Abstract: RTSX-S datasheet SX FPGAs A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144
Contextual Info: v5.1 SX-A Family FPGAs Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops

diode 2U 66

Contextual Info: v5.1 SX-A Family FPGAs Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops

sx08a

Contextual Info: v4.0  SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades

A54SX16A

Contextual Info: v4.0  SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades

22B2 DIODE

Abstract: Theta JC of FBGA A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
Contextual Info: v5.3 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops

Contextual Info: Preliminary GS890DV18D-330/300/250/200/167/133/100 9Mb Σ2x2B4V SigmaQuad SRAM 165-Bump BGA Commercial Temp Industrial Temp 100 MHz–330 MHz 2.5 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

k2333

Abstract: GS8342T GS8342T36
Contextual Info: Preliminary GS8342T08/18/36E-400/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: Preliminary GS81302S08/09/18/36E-333/300/250/200/167 144Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 4M x 36Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS81302T19/37E-400/375 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaCIO DDR-II+ Burst of 2 SRAM 400 MHz–375 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

GS8182S18BD-167

Abstract: GS8182S18BD-200 GS8182S18BD-250 GS8182S18BD-300
Contextual Info: Preliminary GS8182S08/09/18BD-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS81302S08/09/18/36E-333/300/250/200/167 144Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

GS8182S18BD

Contextual Info: Preliminary GS8182S08/09/18BD-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

2032LV

Abstract: TMS3534
Contextual Info: ispLSI 2032V/LV 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 7.5 ns Propagation Delay A1 A2 D Q GLB A6 D Q D Q A5 D Q A3 A4

Contextual Info: Preliminary GS8182R08/18/36BD-333/300/250/200/167 18Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

74AS1004

Abstract: SCYD001 XDS510 XDS510 MPSD 67996-114 ACT8990 74F175 74LVT240 ACT8999 SPDU079A
Contextual Info: JTAG/MPSD Emulation Technical Reference 1994 Printed in U.S.A., December 1994 2617709–9741 revision A SPDU079A JTAG/MPSD Emulation Technical Reference December 1994 SPDU079 Printed on Recycled Paper Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any

ACTEL flashpro datasheet

Abstract: INVERTER 10kW eX256 SCHEMATIC 10kw inverter RT54SX-S FLASHPRO LITE
Contextual Info: v2.0 eX Automotive Family FPGAs Specifications • • • • FuseLock • Design Support from Actel’s Designer Software and Libero Integrated Design Environment IDE • Up to 100% Resource Utilization with 100% Pin Locking • Deterministic Timing

SPDU079A

Abstract: ACT8990 XDS510 MPSD 74AS1004 JTAG(MINI)14 pin 74F175 74LVT240 ACT8999 TL7705A XDS510
Contextual Info: JTAG/MPSD Emulation Technical Reference 1994 Printed in U.S.A., December 1994 2617709–9741 revision A SPDU079A JTAG/MPSD Emulation Technical Reference December 1994 SPDU079 Printed on Recycled Paper Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any

GS8182R08GBD

Contextual Info: Preliminary GS8182R08/18/36BD-333/300/250/200/167 18Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

EX256-TQ100

Contextual Info: Revision 10 eX Family FPGAs Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)