10125 ECL TO TTL Search Results

HD10125

Contextual Info: H D 10125 Quadruple ECL to TTL Translators The H D 10125 is a quad translator for interfacing data and control signals between the ECL section and saturated logic sections of digital systems. The HD 10125 incorpolates differential inputs and Schottky T T L "totem

HD10125

Contextual Info: H D 10125 Quadruple ECL to T T L T ra n s la to rs I PIN ARRANGEMENT The H D 10125 is a quad translator for interfacing data and control signals between the ECL section and saturated logic sections of digital systems. The H D 10125 incorpolates differential inputs and Schottky T T L “totem

10125N

Abstract: 10125F 10125DC 10125-F 10125d
Contextual Info: Philips Components 10125 D ocum ent No. 8 5 3 -0 6 5 8 EC N No. 99799 D ate of Issue J u n e 14, 1990 Gate S tatus Product Specification Quad ECL-to-TTL Translator E C L Products FEATURES ORDERING INFORMATION • Typical propagation delay: 3.5ns • Typical supply current

10125 ecl to ttl

Abstract: 10125f
Contextual Info: Philips Components-Signetics D o cum ent No. 8 5 3 -0 6 5 8 E C N No. 99799 D a te of Is s u e J u n e 14 , 1 9 9 0 S ta tu s P ro d u ct S p e c ific a tio n 10125 Gate Quad ECL-to-TTL Translator E C L P ro d u cts FEATURES • Typical propagation delay: 3.5ns

Contextual Info: FAIRCHILD INTERFACE LEVEL TRANSLATORS Power Dissipation mW Logic/Connection Diagram s +12 to +20 0.0 (+VJ-2.0 +0.4 90 440 G12 6A Dual ECL-TTL +5.0 -5.2 +2.4 +0.4 6.0 375 E15 6B TTL-MOS +5.0 0.0 to -30 Vtap -1-0 <-V)+2.0 z o > UJ Û 1 9112 TTL-H LD TL Hex

11C44

Abstract: 11C58 E106 10125 ecl to ttl 11C24 10124 fairchild mos
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E15 9595 E14 100123 E16 95124/10124/10524 5 (1 1 ) 7 (10) • = 0 = 3 3 (7) eJ?i ¡7 = 0 ^ : 2(6) 4 (8) ;^ 0=^5 (3) (16) (14) 1 4 (2) 1 3 (1) (15) Vcc = Pin 5 V cc a = Pin 6 V ee = Pin 12 G N D = Pin 4 V cc = Pin 9 (6)

D25 connector

Abstract: 10125 ecl to ttl chip resistor R10 GS9002 MC10125P 2N4400 A-302 GS9009 2N4404 EB900
Contextual Info: GENLINX Serial Digital Encoder Board using the GS9002 and GS9009 by Ian Ridpath, Senior Applications Engineer, Video and Broadcast Group APPLICATION NOTE INTRODUCTION This application note describes the construction and implementation of the GENNUM EB-9002/9A Evaluation Board.

Contextual Info: FAIRCHILD INTERFACE LEVEL TRANSLATORS Power Dissipation mW Logic/Connection Diagram s 00 (+V)-2 0 +0 4 90 440 G12 6A Dual ECL-TTL +5 0 -5 2 +2 4 +0 4 60 375 E15 6B +5 0 0 0 to -30 Vtap-1 0 (-V)+2 0 DEVICE NO.(1,2) +12 to +20 Item Supply Voltage V- (Typ)

DC motor 6volt

Abstract: Difference between LS, HC, HCT devices 74 HC Series Logic ICs 74 HC Series ICs CD4504 Cmos 74 HC difference between HC LS series CI 4049 4049bh cd 4050 buffer ic
Contextual Info: Application Notea Interfacing HC/HCT QMOS Logic with Other Families and Various Types of Loads by R. Funk The demand fo r smaller, lighter, electronic equipment that consum es little pow er is constant. And today's logic designers want these qualities matched by digital logic with

mw 137

Abstract: fairchild ECL
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

bb106

Abstract: LM317MP r13-21 LM337 8pin transition lm337 LM337MP AN7910 BB-121-5 BB121 PMI-OP
Contextual Info: SPT AN7910/12 EVALUATION BOARD SIGNAL PROCESSING TECHNOLOGIES APPLICATION NOTE FEATURES CAPABILITIES AND APPLICATIONS • 30 MSPS Conversion Rate • • • • • • • • • • • • • • • On-Board Reconstruction DAC Differential Clock Driver

9624

Abstract: 11C24 11C44 11C58 E106 10125 ecl to ttl
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE I8 9622 17 9621 19 9624 GND [ I 2 Nc Q 3 IN A l C 4 IN A 2 ^ 5 IN A3 Q 6 IN A O Q 7 Vd d L f t •14 □ vcc 13 □ tap 12 □ nc 11 □ in B3 10 J in B2 9 □ in B1 8 □ OUT B 112 9650 110 111 9625 9627 1 GND

10125 ecl to ttl

Abstract: ttl to ecl converter db9f connector connector DB9F connector DB25f datasheet connector DB25f DB25F db9f pcb connector 244M EB9021
Contextual Info: GENLINX II EB9021 Evaluation Board PRELIMINARY INTRODUCTION A PLD is provided primarily to interface to the Flag Port of the GS9021 and extract the Ancillary, Full Field, and Active Picture error flags. The PLD is designed to cycle the S[1:0] inputs of the GS9021, read and demultiplex the output error

i 7814 hs

Abstract: LM317MP HP3325A C2958 Fluke 6060B C5612-11 C2028 ALLEN-BRADLEY RESISTOR temperature 270 IN4002 diode TbA 2025
Contextual Info: SPT AN7810/14 EVALUATION BOARD SIGNAL PROCESSING TECHNOLOGIES FEATURES CAPABILITIES AND APPLICATIONS • 20 and 40 MSPS Conversion Rates • Evaluation of SPT7810 and SPT7814 • Engineering System Prototype Aid • Differential Clock Driver • Incoming Inspection Tool

h 9645

Abstract: Level Translators 9644 10125 ecl to ttl B1 9A 9645 fairchild Quad TTL to MOS Driver 8T26 11C44 11C58
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE RECEIVER ENABLE RECEIVER O UT A DRIVER IN C DRIVER IN C 155 9641/26S11 Vcc G ND ^ 14 RECEIVER □ 0UTD TJ IND “ I DRIVER 3 STROBE BUS D RECEIVER OUT D H DRIVER IND ^ STROBE ^ BUS C ^ 1 DRIVER i” 1 RECEIVER

Contextual Info: Interconnection Systems Selection Guide 82750 Opto Electronic Devices Revised 7-95 FSD Multimode Transceiver Product Facts • Fiber Distributed Data Interface FDDI compliant ■ 22-pin multisourced package ■ Compatible with raised 10H, 10K and 100K ECL

9582 Fairchild

Abstract: 95H28 11C44 11C58 11C24 95H29 E106 MOS Clock Driver 9582 95H28 Fairchild
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E21 11C58 E22 9582 E23 95115/10115/10515 9 5 (8)4 cx 1 1 - .¡¿ .1 4 2 Q Vex INPUT FILTER — (14) 10 ( 13)9 7 (11) 6 (10) (16) 12 ( 1) 13 15 (3) 14 (2) 14 BIAS FILTER 12 13 13 3 (7) 2 (6) U 0 -6 11 (15)

micrologic

Abstract: 9094 Quad TTL to MOS Driver DIGITAL-DTL dtl 948 951 monostable 951 Monostable Multivibrator 11C24 11C44 11C58
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-DTL G7 1812 G8 9157, 9158 □ ,4 □ 13 □ 12 G9 933 ¡ 3 14 * L 3 C 4 L 3 " J 1 0 s L 7L Vcc = Pin 14 G N D = Pin 7 N o c o n n ec tio n req uired to V g c P in 1 4 . Vcc = Pin 14 G N D = Pin 7 G10 946, 949 Vcc = Pin 14

signetics 10107

Abstract: decoder active high outputs signetics 10131 ECL 10131 ECL 10102 ECL 10105
Contextual Info: LANSDALE SEMICONDUCTOR bOE J> I 5 3 ^ 3 0 3 O O O Q S m 0^3 « L T E Rating Supply Voltage - Vcc Input Voltage - Vjn SIGNETICS INTEGRATED CIRCUITS Output Source Current 10K ECL Storage Temperature Range Emitter-coupled logic is the fastest logic technology available

H 9645

Abstract: 10125 ecl to ttl m 9625 11C24 4049B 4050B 4104B C312 MA7151 11c44
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE ?h :ky 161 9646 160 9646 159 9645 [16 Vcc 1 15 NC E 2 ncQ 3 O UT A 4 NC ^ 5 IN A Q 6 NC Q 7 IJ O U T D 14 ^IND 13 12 JE , 11 ?0 IN C 3 O UT C 9 3 NC 14 □ V eci 13 □ nc 12 ^ OUT B 11 □ nc 1 N C [^ O UT A 3

cc770

Abstract: AMCC Q700
Contextual Info: Q /ï^ c j 004958 G/n C. DEVICE SPECIFICATION APPLIED M IC R O C IR C U IT S C O R PORATION Q700 SERIES ECL/TTL LOGIC ARRAYS FEATURES VARIOUS ARRAY SIZES 250, 500, 1000 equivalent gate versions to support various circuit requirements. VERY HIGH SPEED 0.5 to 0.9 ns average gate delay within the internal array.

Contextual Info: H D 1012S Quadruple ECL to TTL Translators The H D 1 0 1 2 5 is a quad translator fo r interfacing data and control signals •PIN ARRANGEMENT between the E C L section and saturated logic sections o f digital systems. The H D 1 0 1 2 5 incorpolates differential inputs and S cho ttky T T L "totem

mm74hc

Abstract: CMOS TTL Logic Family Specifications FAIRCHILD MM74HC compared CMOS TTL Logic Family Specifications MM74HC fairchild MM74HC 16 pin MM74HC pin configuration CMOS Logic Family Specifications CD4000 series applications cmos logic databook
Contextual Info: Fairchild Semiconductor April 1998 This application note pertains to the VHC Speciality Function devices only listed in this section of the databook . These devices are direct pin, function and spec replacements for their MM74HC counterparts. On many occasions it might be necessary to interface

QH1500

Abstract: DIODE BJE ECL100K Q1500A QH1500A MSI IC decoder 6 input or gate 68 LCC
Contextual Info: APPLIED MICRO CIRCUITS bfc. D eJ □ßfiTOOE OOOGObS b DEVICE SPECIFICATION r ? T - V O .- jJ- t e APPLIED MICRO CIRCUITS CORPORATION Q1500 SERIES LOGIC ARRAYS FEATURES *w TWO ARRAY SIZES 1500 and 1700 equivalent gate densities are available in the Q1500A and QH1500A respectively.