102H CBE Search Results

Contextual Info: 23 HARRIS H S P 4 3 1 6 8 Dual FIR Filter A u g u st 1992 Features D escription • Tw o The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows

ZL50012QCG1

Abstract: MS-026 ZL50012 STO10
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features • April 2006 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

MS-026

Abstract: ZL50012 TFPW0 sto8b
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

DS5722

Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

MS-026

Abstract: ZL50012
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

MS-026

Abstract: ZL50012 philips e3 STO11 ci 116h 4094m
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection

BC1211

Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

md 5408

Abstract: SCAT CODE 4448 PCIM 164 GE 8352 HD 5888 7830A 8352 GE ge 5216 transistor 8mx32 simm 72 pin ic 8237 dma controler
Contextual Info: STPC CLIENT  Multimedia PC on a Chip • POWERFUL X86 PROCESSOR ■ 64-BIT 66MHz BUS INTERFACE ■ 64-BIT DRAM CONTROLLER ■ SVGA GRAPHICS CONTROLLER ■ UMA ARCHITECTURE ■ VIDEO SCALER ■ VIDEO OUTPUT PORT ■ VIDEO INPUT PORT ■ CRT CONTROLLER ■

GR-1244-CORE

Abstract: MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512-ch DX with on-chip DPLL Data Sheet Features VDD • • • Applications • • • • • Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers VSS

32.768Mhz oscillator

Abstract: FOX 20.000 MHZ GR-1244-CORE MS-026 ZL50011 tfk8
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

star delta auto trans wiring diagram

Abstract: md 5408 VIDEO DISPLAY CONTROLLER CD 5888 CD 5888 CB SCAT CODE 4448 intel Chipset CRB Schematics 452 s90 7830A 83610 pir 815
Contextual Info: STPC CLIENT Multimedia PC on a Chip • POWERFUL X86 PROCESSOR ■ 64-BIT 66MHz BUS INTERFACE ■ 64-BIT DRAM CONTROLLER ■ SVGA GRAPHICS CONTROLLER ■ UMA ARCHITECTURE ■ VIDEO SCALER ■ VIDEO OUTPUT PORT ■ VIDEO INPUT PORT ■ CRT CONTROLLER ■ 135MHz RAMDAC

Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • September 2011 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information ZL50011/GDC 144 Ball LBGA Trays ZL50011QCG1 160 Pin LQFP* Trays, Bake & Drypack

GR-1244-CORE

Abstract: MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

GR-1244-CORE

Abstract: MS-026 ZL50011 11CH marking
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

filter FP1P

Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0

GR-1244-CORE

Abstract: MS-026 ZL50010
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

ZL50010QCG1

Abstract: GR-1244-CORE MS-026 ZL50010 32CH1
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0

GR-1244-CORE

Abstract: MS-026 ZL50010 TFPW0
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

FOX 20.000 MHZ

Abstract: LMT 324 slv ca2 GR-1244-CORE MS-026 ZL50010 STO14 tfk8k
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

ZL50010

Abstract: TFR1M GR-1244-CORE MS-026
Contextual Info: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15

x86 series

Abstract: n439 10h13 stpcc0166 schematics IBM 1161 STPCD01 117CP
Contextual Info: STPC CLIENT  PC Compatible Embeded Microprocessor • POWERFUL X86 PROCESSOR • 64-BIT 66MHz BUS INTERFACE • • 64-BIT DRAM CONTROLLER SVGA GRAPHICS CONTROLLER • • UMA ARCHITECTURE VIDEO SCALER • VIDEO OUTPUT PORT • VIDEO INPUT PORT • •

TXM TX 2E

Abstract: 7296 029H 026H md 5408 BT 2323 M ic pin configuration x86 series sil1101 ACES RAMDAC
Contextual Info: STPC INDUSTRIAL  PC Compatible Embeded Microprocessor PRELIMINARY DATA • POWERFUL X86 PROCESSOR ■ 64-BIT BUS ARCHITECTURE ■ 64-BIT 66MHz DRAM CONTROLLER ■ SVGA GRAPHICS CONTROLLER ■ 135MHz RAMDAC ■ UMA ARCHITECTURE ■ TFT DISPLAY CONTROLLER