1048 Search Results

Contextual Info: SMJ416160, SMJ418160 1048576-WORD BY 16-BIT HIGH-SPEED DRAM 1 SGMS720A - APRIL 1995 - REVISED JUNE 1995 XXX PACKAGE TOP VIEW ACCESS ACCESS ACCESS TIME TIME TIME '41x160-60 41x160-70 '41x160-80 • • • • • • • • tRAC MAX 60 ns 70 ns SO n* *CAC

27A6

Contextual Info: TMS28F210 1048576-BIT FLASH MEMORY I SMJS210B - DECEMBER 1892 - REVISED JUNE 1995 N PACKAGE TOP VIE W Pin Compatible With Existing 1-Megabit EPROMs All Inputs/Outputs TTL Compatible Vcc Tolerance ±10% Maximum Access/Minimum Cycle Time ’28F210-10 100 ns

Contextual Info: TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY S M K S 891C - A U G U S T 1996 - R EVISED O C TO BE R 1997 This data sheet is applicable to TMS418160As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section.

SMOS182

Contextual Info: TMS626802, TMS636802 1048576-WORD BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS182 - FEBRUARY 1994 TM S626802 LVTTL DGE PACKAGE (TO P VIE W ) 3.3-V Power Supply (10% Tolerance) Two Banks for On-Chip Interleaving (Gapless Accesses) vcc [ 1

C1055

Abstract: CLV1052M VCOs
Contextual Info: CLV1052M 9939 Via Pasar • San Diego, CA 92126 TEL 619 621-2700 FAX (619) 621-2722 VOLTAGE CONTROLLED OSCILLATOR Rev A1 PHASE NOISE (1 Hz BW, typical) FEAT URES • Frequency Range: 1048 - 1058 MHz • Tuning Voltage: 0.5-4.5 Vdc • MINI-14MS-L - Style Package

DIP32

Abstract: LC371100SP SM-10 SANYO DL
Contextual Info: I Ordering number : ENÎ8 50B7A CMOS LSI No. 5K 5087A SAMYO LC371100SP, SM-10/LC37110OSP, SM-20LV 1 MEG 131072 wordsx 8 bits Mask ROM Internal Clocked Silicon Gate Preliminary Overview Package Dimensions The LC371100SP, SM-10 and LC371100SP, SM-20LV are 1048576-b it M ask Program m able Read Only

Contextual Info: SPECIFICATION SHEET RS Stock No. 104834 DRAWING - 1 U nit : mm Bulb Type 1. Structure Bulb D iam eter Length Base Type Voltage 2. Design Characteristics Amperage F ilam ent Type T3 1/4 Clear 01O.OMax. 28.0Max E10. 24V 120mA±10% Vacuum type Lum inous Flux

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEN T2 DEI 4 4IikiE03 0010404 S > HD74HC298 92D 10484 # Quad. 2-input Multiplexers with storage) PIN ARRANGEMENT This circuit is controlled by the signals word select and clock. When the word select input is taken low w ord 1 (A 1, B i,

Contextual Info: HITACH I/ L O G I C / A R R A YS/MEH ^5 HD74HC292 HD74HC294 This device divides the j>Ê| 44TL.S03 00104fll □ 92D 10481 incoming clock frequency by a | PIN ARRANGEMENT •H D 7 4 H C 2 9 2 inputs. It has tw o Clock inputs, either o f which m ay be used as a clock in hib it. The device also has an active-low Reset,

hn62308

Abstract: HN62308B
Contextual Info: HN62308B Series 1048576 x 8-Bit CMOS MASK Programmable Read Only Memory • DESCRIPTION The HN62308B is a 8-Mbit CMOS mask-programmable ROM organized as 1048576-words x 8-bits. Realizing low power con­ sumption, this memory is allowed for battery operation. In addition,

RENESAS tft application notes

Abstract: R1LV1616R R1LV1616RBG-5S R1LV1616RSA-5S uTSOP
Contextual Info: R1LV1616R Series 16Mb Advanced LPSRAM 1M wordx16bit / 2M wordx8bit REJ03C0101-0300Z Rev.3.00 2007.08.28 Description The R1LV1616R Series is a family of low voltage 16-Mbit static RAMs organized as 1048576-words by 16-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies.

Contextual Info: Lattice ispLSI and pLSI 1048E ; Semiconductor I Corporation High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC O u tpu t R outing Pool — 8,000 PLD Gates | | O u tpu t R outing Pool ü m u lü lü llS i!

matsua lt48 digital quartz timer

Abstract: Matsushita lt48 timer Matsua lt48 timer matsushita lt48 digital quartz timer Matsua timer PM48 Matsushita timer PM48 LT48 digital quartz timer AT8-DF8K Matsushita lt48w twin timer lc48
Contextual Info: ’06–’07 Timers/Time Switches/Counters/Hour Meters Timers/Time Switches/Counters/Hour Meters ’06–’07 Please contact . Matsushita Electric Works, Ltd. Automation Controls Business Unit Head Office: 1048, Kadoma, Kadoma-shi, Osaka 571-8686, Japan

BM-11x88MD

Abstract: BM-10288MD-A BM-10288ND-A BM-10488MA-A BM-10488MD-A BM-10488NA-A BM-10488ND-A BM-10688MA-A BM-10688MD-A BM-10688NA-A
Contextual Info: Single Color 8x8 Dot Matrix Displays Part No. Digit Size 1.20 High 3.0 Column Common Anode Column Common Cathode BM-10288MD-A BM-10288ND-A GaP/ GaP/ Yellow Green 568 30 80 30 150 2.1 2.5 9.0 BM-10488MD-A BM-10488ND-A GaAsP/GaP/ Hi-Eff.Red 635 45 80 30 150

Contextual Info: HN62448N Series 524288-word X 16-bit/1048576-word x 8-bit CMOS Mask Programmable ROM HITACHI ADE-203-385B Z Rev. 2.0 Oct. 2 1 ,1996 Description The Hitachi HN62448N is a 8-Mbit CMOS mask-programmable ROM organized either as 524288-word by 16-bits or as 1048576-words by 8-bits. And a high speed access of 100/120 ns is the most suitable to the

Contextual Info: HN62448 Series 524288-word x 16-bit/1048576-word x 8-bit CMOS Mask Programmable ROM HITACHI ADE-203-397B Z Rev. 2.0 Oct. 2,1996 Description The Hitachi HN62448 is a 8-Mbit CMOS mask-programmable ROM organized either as 524288-words by 16-bits or as 1048576-words by 8-bits. And a high speed access of 100/120 ns is the m ost suitable to th

Contextual Info: FUJITSU ECL 16384-BIT BIPOLAR RANDOM ACCESS MEMORY 10484AAugust 1988 Edition 2.0 16384-BIT BIPOLAR ECL RANDOM ACCESS M EM ORY The Fujitsu MBM 10484A is fu lly decoded 16384-bit ECL read/write random access memory designed fo r high-speed scratch pad, control and buffe r storage

Contextual Info: HN29WT800/HN29WB800 Series 1048576-word x 8-bit / 524288-word x 16-bit CMOS Flash Memory HITACHI ADE-203-537 Z Preliminary - Rev. 0.0 J u n .14,1996 Description The Hitachi HN29WT800 Series, HN29WB800 Series are 1-Mword x 8-bit/512-kword x 16-bit CMOS Flash Memory with DINOR (Divided bitlineNOR) type memory cells, thatrealize programming and erase

Contextual Info: HM51W16160 Series HM51W18160 Series 1048576-word x 16-bit Dynamic RAM HITACHI ADE-203-635C Z Rev. 3.0 Feb. 21,1997 Description The Hitachi HM51W16160 Series, HM51W18160 Series are CMOS dynamic RAMs organized as 1,048,576-word x 16-bit. They employ the most advanced CMOS technology for high performance and

TMS626812

Contextual Info: TMS626812 1048576-WORD BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY _ SMOS687A -JULY 1 9 9 6- REVISED APRIL 1997 • • • Organization . . . 1M x 8 x 2 Banks 3.3-V Power Supply ± 10% Tolerance Two Banks for On-Chip Interleaving

S891C

Abstract: SS828
Contextual Info: TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY S M K S891C -A U G U S T 1996-R E V IS E D OCTOBER 1997 This data sheet is applicable to TMS418160As symbolized by Revision “E ” and subsequent revisions as described in the device symbolization section.

Contextual Info: Preliminary W 21010A inbond Electronics Corp. 1M x 1 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W21010A is a high speed, low power C M O S static RAM organized as 1048576 x 1 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high

Contextual Info: TMS28F008Axy,TMS28F800Axy 1 048 576 BY 8-BIT/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SM JS851A-NO VEM BER 1997 - REVISED MARCH 1998 • Organization . . . 1048576 By 8 Bits 524288 By 16 Bits • Array-Blocking Architecture - Two 8K-Byte/4K-Word Parameter Blocks

Contextual Info: HM5118160BI Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-580A Z Rev. 1.0 May. 20, 1996 Description T he H itachi H M 5118160B I is a C M O S dynam ic R A M organized as 1,048,576-w ord x 16-bit. It em ploys the m ost advanced C M O S technology fo r high perform ance and low pow er. T he H M 5118160B I offers