105002B Search Results

ITE 8512

Abstract: jrm A45 RD2 earth leakage relay TN2E-5V T7903FC 2768B tm4101 Aromat tn2e STT 3 SIEMENS T7903
Contextual Info: Preliminary Data Sheet April 1997 m icroelectronics group Lucent Technologies Bell Labs Innovations T7903 ISA Multiport Wide Area Connection ISA-MWAC Device F eatu res • Three wide area connection ports. Each port can be configured as a basic rate ISDN TE or NT or as

Contextual Info: Lucent Technologies Bell Labs Innovations ATT3000 Series Field-Programmable Gate Arrays Features The ORCA Foundry for ATT3000 development sys­ tem provides automatic place and route of netlists. Logic and timing simulation are available as design verification alternatives. The design editor is used for

Contextual Info: Data Sheet September 1995 m A T& T Microelectronics DSP1616-X11 Digital Signal Processor 1 Features 2 Description • Optimized for digital cellular applications with a bit manipulation unit for higher signal coding efficiency ■ 38 ns and 33 ns instruction cycle

DSP16A

Abstract: cis linear 2400 HSM144DD HSM144LD HSM144PD T7525 Rockwell V.17 Training EQUALIZER ERROR FILTER SCRAMBLE SAMPLE marking ma4 wedsp16a
Contextual Info: A T & T MELCC I C btE II • DDSÜDSb DDPTtbl 1R8 « A T T ä ATsT June 3" 1993 ^ M ic r o e le c tr o n ic s AT&T HSM144xD Data Pump Chip Sets (14,400 bits/s Data/FAX, ROM Code MA) Introduction Features The AT&T HSM144xD Data Pump Chip Sets allow modem designers to build high-speed, fully-featured

Contextual Info: Data Sheet June 1999 m ic r o e le c t r o n ic s group Lucent Technologies Bell Labs Innovations LG1600KXH Clock and Data Regenerator Features • Integrated clock recovery and data retiming ■ Surface-mount package ■ Single ECL supply ■ Robust FPLL design

lt228

Abstract: b433 resonator CD 4017 PIN DIAGRAM SDL 4007 TT 2146 4043-C DB3C 828 F3L3 AB14C wy 413
Contextual Info: Preliminary Data Sheet i uy ü AT&T Microelectronics DSP1604/06 Digital Signal Processor •I 1 Features 2 Description ■ For 5 V operation: — 25 ns instruction cycle time 40 MIPS — 30 ns instruction cycle time (33 MIPS) ■ For 3.3 V operation: — 31.25 ns instruction cycle time (32 MIPS)

JW050A1-E Lucent

Abstract: JW050A1-E jw075a1 JW050A1
Contextual Info: Data Sheet March 1998 Lucent Technologies Bell Labs Innovations JW050A1-E and JW075A1-E Power Modules: dc-dc Converters; 36 to 75 Vdc Input, 5 Vdc Output; 50 W to 75 W Features • Small size: 61.0 mm x 57.9 mm x 12.7 mm 2.40 in. x 2.28 in. x 0.50 in. ■ High power density

6N0 953 235

Contextual Info: Preliminary Data Sheet microelectronics group Lucent Technologies Bell Labs Innovations ORCA OR3Cxx 5 V and OR3Txxx (3.3 V) Series Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 nm 4-level metal technology, with a migration plan to 0.25 urn

ks 4290 industrial controller

Abstract: AKA NF 028 ATT2C12 ATT ORCA fpga ATT2C08 ATT2C15 52833 trw 2015 ptc ei 8n CODE PJ 62-00
Contextual Info: Preliminary Data Sheet January 1995 AT&T Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features • High density: 3,500 to 26,000 usable gates ■ High I/O: up to 384 usable I/O ■ High-performance 0.5 (xm CMOS technology