109B Search Results

HD74LVC240A

Abstract: DSA003634
Contextual Info: HD74LVC240A Octal Buffers / Line Drivers with 3-state Outputs ADE-205-109B Z 3rd Edition December 1996 Description The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four

MS122123

Contextual Info: INCH-POUND MIL-M-38510/109B 28 May 2004 SUPERSEDING MIL-M-38510/109A 18 September 1980 MILITARY SPECIFICATION MICROCIRCUITS, LINEAR, PRECISION TIMERS, MONOLITHIC SILICON Reactivated after 28 May 2004 and may be used for either new or existing design acquisitions.

HD74LVC240A

Abstract: Hitachi DSA00229
Contextual Info: HD74LVC240A Octal Buffers / Line Drivers with 3-state Outputs ADE-205-109B Z 3rd Edition December 1996 Description The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four

Contextual Info: HD74LVC240A Octal Buffers / Line Drivers with 3-state Outputs HITACHI ADE-205-109B Z 3rd Edition December 1996 Description The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls

Hitachi DSA00104

Abstract: HD74LVC240A
Contextual Info: HD74LVC240A Octal Buffers / Line Drivers with 3-state Outputs ADE-205-109B Z 3rd Edition December 1996 Description The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1* and 2*). Each enable independently controls

Hitachi DSA00280

Contextual Info: HD74LVC240A Octal Buffers / Line Drivers with 3-state Outputs ADE-205-109B Z 3rd Edition December 1996 Description The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four

ic 109b

Abstract: BAT54 LM1770 LM3370 LP5550 SIGNAL PATH designer
Contextual Info: 8009 Power Designer 109b 5/31/06 12:13 PM Page 1 POWER designer Expert tips, tricks, and techniques for powerful designs No. 109 Advanced Topics in Powering FPGAs Feature Article.1-7 Step-Down DC-DC Converter with Dynamic Voltage Scaling.2

UFF 50 02

Contextual Info: HD74LVC240A Octal Buffers / Line Drivers with 3-state Outputs HITACHI ADE-205-109B Z 3rd Edition December 1996 Description The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls

HD74LVC240A

Abstract: HD74LVC240AFPEL HD74LVC240ATELL
Contextual Info: HD74LVC240A Octal Buffers / Line Drivers with 3-state Outputs REJ03D0351–0400Z Previous ADE-205-109B (Z Rev.4.00 Jul. 26, 2004 Description The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is an inverting

ic 109b

Abstract: MG100M2YK1 Di 762 transistor transistor B 764
Contextual Info: MG100M2YK1 GTR MODULE SILICON NPN TRIPLE DIFFUSED TYPE Unit in mm HIGH POWER SWITCHING APPLICATIONS. MOTOR CONTROL APPLICATIONS. 6-FAST-ON-TAB t 110 JAPAN 3-M5 FEATURES: 4 -065±C13 . The Collector is Isolated from Case. to . 2 Power Transistors and 2 Free Wheeling

transistor jc 817

Abstract: MG150q2yk1 470G jc 817
Contextual Info: GTR MODULE SILICON NPN TRIPLE DIFFUSED TYPE MG150Q2YK1 TENTATIVE DATA HIGH POWER SWITCHING APPLICATIONS. MOTOR CONTROL APPLICATIONS. Unit in mm fi-FAST-ON-TAB t 1 1 0 FEATURES: \ JAPAN » 3~M5 P_ 0 & 5 ÌIO .3 . The Collector is Isolated from Case. . Power Transistors and 2 Free Wheeling

AN6019

Abstract: PAC10 1GM1
Contextual Info: ispPAC 10 Features Functional Block Diagram • IN-SYSTEM PROGRAMMABLE ISP ANALOG CIRCUIT — Four Instrument Amplifier Gain/Attenuation Stages — Signal Summation (Up to 4 Inputs) — Precision Active Filtering (10kHz to 100kHz) — No External Components Needed for Configuration

a00u

Abstract: Z32100 STK 411 230 WE32100 ALI m7 101b BUX 707 z32101 Z32103 BUDA lo4p
Contextual Info: Y " P ro d u ct S pecification January 1987 Z32103 D R A M C O N TR O LLER DESCRIPTION T he Z32103 D R A M Controller provides address multiplexing, access and cycle time management, and refresh control for dynam ic random access m emory DRAM . It provides, in a single chip,

Contextual Info: C&K MIL Series 1-4 Pole Miniature Right Angle Rotary Switches Typical Applications • Telecom switching equipment • Military communications 5 banks per switch • Instrumentation • Totally sealed insert molded contacts • Medical monitors Features/Benefits

CR250J

Abstract: CR250J24 CR250J-8 CR150DM CR150DM-10 CR150DM-12 CR150DM-24 CR150DM-32 CR150DM-36 CR150DM-4
Contextual Info: - 50 - m ss « CR150 DM— 10 CR150 DM— 12 CR150 DM— 16 CR150DM-20 CR150 DM— 2 4 CRI 50DM—? CR ì 50 DM— 3 2 CRI 50 DM— 3 6 CR150 DM— 4 CR150DM-6 CR150DM-8 CR250DP-4 CR250DP-6 CR250DP-8 CR250J-10 CR2 50 J— 12 CR250J— 16 CR2 50 J— 20 CR250J-24

SY 356

Abstract: sy 171 S6146G SF0R1A42 Sfor1a42 DRA01B DRA01C DRA01E DRA03TB DRA03TC
Contextual Info: - Si 1 Vth 1. 50 1. 50 1. 40 1. 40 1.40 2. 00 2. 00 2. 00 2. 00 1. 60 1, 60 1. 60 1. 60 1. 60 1. 60 1. 60 1. 60 2. 50 2. 50 2. 50 2. 00 2.00 2. 00 2. 00 1 . 60 1 . 60 1 . 60 1 . 60 1 . 60 1. 60 1. 60 1. 60 1. 50 1. 50 1. 50 1 . 60 2. 30 Tj °C 25 25 25 25

CR500AL-8

Abstract: FT100DM-10 FT100DM-12 FT100DM-16 FT100DM-20 FT100DM-24 FT100DM-28 FT100DM-32 FT100DM-36
Contextual Info: - W dv/dt min * V g d (min) Vth Vg t (V) 1. 35 2.00 2.00 2. 00 2.00 2. 00 2. 00 2.00 2.00 2. 00 2. 00 2.00 1.80 1. 80 1. 80 1. 80 1. 80 1.80 1.80 1.80 1. 80 1. 80 1. 80 1. 50 1. 50 1. 50 1.50 1. 50 1. 50 1. 50 1.50 1. 90 1. 90 1.90 2.20 2. 20 2.20 2. 20

Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb2 SRAM 36Mb QDR SRAM 2-WORD BURST MT54V2MH18A MT54V1MH36A Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE

Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, Pipelined DDRb2 SRAM 36Mb DDR SRAM 2-Word Burst MT57V2MH18A MT57V1MH36A Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times Pipelined, double data rate operation

SMSC LAN911x

Abstract: LAN911x CRC32 LAN9115 LAN9116 LAN9117 LAN9118 circuit diagram of queuing with seven segment
Contextual Info: AN 12.12 LAN9118 Family Programmer Reference Guide 1 Introduction This application note describes how to successfully develop a network device driver for LAN9118 Family products. It covers device features, software design techniques, network operating system

heat sensor with fan cooling using ic LM 741

Abstract: 9GV0412P3 smr 40100 San Ace 120L 109R0624J402 109R1212H101 121 M 221 03 9cr0412s sanyo denki brushless p3 Sanyo Denki dc fan 109r0612t4h12
Contextual Info: COOLING SYSTEM San Ace Products Information 2006 ver.2 C O N T E N T S Technical Material ･････････････････････ p.3 Product Guide Instruction Manual for Fan ‥‥‥‥‥ p.20 Part Numbering System ‥‥‥‥‥‥ p.22

triac zd 607

Abstract: 1n5204 CA2820 TRW 2N4427 equivalent bfr91 2N6823 842 317 SO8 BD243 PINOUT BD529 bf506 BF845
Contextual Info: MASTER SELECTION GUIDE EUROPEAN SUPPLEMENT This is the European supplement to the USA edition of the Master Selection Guide, SG73/D REV 3. It should be read along with the USA edition. The supplement carries amendments to sections 1 and 5 in the USA edition.

RX-2C G

Abstract: tx2c transmitter TX 2E 1240 picosecond tx-2b equivalent Gigabyte 848 TX-2B RX-2B ROSENBERGER RX_2B XENPAK70
Contextual Info: Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide UG076 v4.1 November 2, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

ISL9504

Abstract: b6886 PP3V42G3H NVIDIA G84m ISL9504BCRZ C8050 12v p66 apple k50 apple M75 MLB 820-2101 PP3V42
Contextual Info: 8 6 7 2 3 4 5 CK APPD OROYA 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 1 REV ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE ? ? ? ? DATE ? 03/20/2007 - DVT