10BITWIDE Search Results

Contextual Info: TLK2218 www.ti.com SLLS734 – FEBRUARY 2007 8-PORT GIGABIT ETHERNET TRANSCEIVER FEATURES • • • • • • • • • • • Eight 1.0- to 1.3-Gigabits Per Second Gbps Synchronizable Transceivers Haft-Rate Operation (0.5 to 0.65 Gbps) Low Power Consumption <1.3 W Typical at

Contextual Info: TLK4015 QUAD 0.6 to 1.5 Gbps TRANSCEIVER SLLS541B − DECEMBER 2002 − REVISED JULY 2006 D Hot Plug Protection D Quad 0.6 to 1.5 Gigabits Per Second Gbps Serializer/Deserializer D Independent Channel Operation D 2.5-V Power Supply for Low-Power D D D D

N1084

Abstract: 1575p 170M ADV7320 CCIR-656 PAL-60 T-1004 ADV7321 274M-10
Contextual Info: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs ADV7320/ADV7321 High definition HD input formats 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb Fully compliant with SMPTE 274M (1080i, 1080p @ 74.25 MHz) SMPTE 296M (720p) SMPTE 240M (1035i)

Contextual Info: TNETE2201B 1.25ĆGIGABIT ETHERNET TRANSCEIVER ą ąą SLLS367C − JUNE 1999 − REVISED JUNE 2004 D 1.25 Gigabits Per Second Gbps Gigabit D D D D Ethernet Transceiver Based on the P802.3Z Specification Transmits Serial Data up to 1.25 Gbps Operates With 3.3-V Supply Voltage

ADV7197EB

Abstract: ADV7197EB Rev. B 720P ADV7197 ADV7197KST RS-170 RS-343A tri-level sync generator OP AMP 748 MR520
Contextual Info: a FEATURES INPUT FORMATS YCrCb in 2 ؋ 10-Bit 4:2:2 or 3 ؋ 10-Bit (4:4:4) Format Compliant to SMPTE274M (1080i), SMPTE296M (720p) and Any Other High-Definition Standard Using Async Timing Mode RGB in 3 ؋ 10-Bit 4:4:4 Format OUTPUT FORMATS YPrPb HDTV (EIA-770.3)

Broken Conductor Detection for Overhead Line Distribution System

Abstract: verilog code for CORDIC to generate sine wave verilog code for cordic algorithm for wireless la TXC 13.56 sma diode h5c intel 945 motherboard schematic diagram 2005Z fet k241 EARTH LEAKAGE RELAY diagram schematic diagram for panasonic inverter air cond
Contextual Info: Stratix GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SGX5V1-1.2 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

mercury motherboards regulator ic

Abstract: TRANSISTOR SUBSTITUTION DATA BOOK 1993 CORDIC to generate sine wave fpga verilog code for CORDIC to generate sine wave verilog code for cdma transmitter vhdl code for cordic intel atom microprocessor verilog code for 2D linear convolution filtering mercury computer motherboard sumida inverter IV
Contextual Info: Stratix Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V2-3.5 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

Contextual Info: TNETE2201B 1.25ĆGIGABIT ETHERNET TRANSCEIVER ą ąą SLLS367C − JUNE 1999 − REVISED JUNE 2004 D 1.25 Gigabits Per Second Gbps Gigabit D D D D Ethernet Transceiver Based on the P802.3Z Specification Transmits Serial Data up to 1.25 Gbps Operates With 3.3-V Supply Voltage

Contextual Info: 19-2130; Rev 2; 11/10 KIT ATION EVALU ABLE AVAIL 10-Bit Bus LVDS Deserializers The MAX9206/MAX9208 deserializers transform a highspeed serial bus low-voltage differential signaling BLVDS data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with serializers such as the MAX9205/MAX9207, which generate a serial BLVDS signal from 10-bit-wide parallel

A4989

Abstract: GMII VLAN Tag A4954 A493* A495 IXF1002 A4941 a4950 A4998 A4935 A4972
Contextual Info: Intel IXF1002 Dual Port Gigabit Ethernet Controller Datasheet Product Features The Intel® IXF1002 Dual Port Gigabit Ethernet Media Access Controller MAC , provides two independent 1000 Mb/s intelligent, high-performance Media Access Control (MAC) ports. It includes Gigabit Physical Coding

Contextual Info: TNETE2201 1.25-GIGABIT ETHERNET TRANSCEIVER SLLS267D – JUNE 1997 – REVISED FEBRUARY 1999 D D D D D 1.25 Gigabits Per Second Gbps Gigabit Ethernet Transceiver Based On the P802.3Z Specification Transmits Serial Data Up to 1.25 Gbps Operates With 3.3-V Supply Voltage

Contextual Info: TLK2208 8ĆPORT GIGABIT ETHERNET TRANSCEIVER SLLS556B − DECEMBER 2002 − REVISED NOVEMBER 2003 D Eight 1.0- to 1.3-Gigabits Per Second D D D D D D D D D D Gbps Synchronizable Transceivers Low Power Consumption <1.3 W at 1.25 Gbps IEEE 802.3z Gigabit Ethernet Compliant

P802

Abstract: TNETE2201B TNETE2201BPHD TNETE2201BPHDG4 TNETE2201BPJD TNETE2201BPJDG4 TNETE2201BPJDR TNETE2201BPJDRG4
Contextual Info: TNETE2201B 1.25ĆGIGABIT ETHERNET TRANSCEIVER ą ąą SLLS367D − JUNE 1999 − REVISED AUGUST 2007 D 1.25 Gigabits Per Second Gbps Gigabit D D D D Ethernet Transceiver Based on the P802.3Z Specification Transmits Serial Data up to 1.25 Gbps Operates With 3.3-V Supply Voltage

Contextual Info: T R T I Q O U I N T S E M I C O N D U C T O R , I N C » G A9103 265 Mbaud Fibre Channel ENDEC Features designed to s u p p o rt the req uirem e nts o f Fibre Channel Standard X3T9.3. The G A9103 is an e ncod er/d e co d er ENDEC integrated c irc u it w hich

A115-A

Abstract: AM29841 C101 CY54FCT841T CY74FCT841T
Contextual Info: CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 D D D D D D D D D D D D CY54FCT841T . . . D PACKAGE CY74FCT841T . . . P, Q, OR SO PACKAGE TOP VIEW Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic

100BASE-FX

Abstract: AA23
Contextual Info: DIGITAL Semiconductor 21440 Multiport 10/100Mbps Ethernet Controller Data Sheet Order Number: EC–R471A–TE Revision/Update Information: This is a new document. Digital Equipment Corporation Maynard, Massachusetts http://www.digital.com/info/semiconductor

toshiba laptop schematic diagram

Abstract: acer motherboard circuit diagram MAX1270 C source code MAX11871 mp 9141 es dc-dc lm324 pwm speed motor 220v DC MOTOR SPEED CONTROLLER schematic ACER laptop schematic diagram L-band down converter for satellite tuner wideband acer laptop MOTHERBOARD Chip Level MANUAL acer laptop motherboard circuit diagram
Contextual Info: Welcome to the Maxim Full-Line Data Catalog. We hope you find this CD-ROM a helpful tool for selecting the best Maxim IC for your design. This CD-ROM contains: The Maxim Full-Line Data Catalog The menu to the left of this page lists the available documents. Use the small

st4850

Abstract: 504MH
Contextual Info: ANALOG DEVICES CMOS, 240 MHz Triple 10-Bit High Speed Video DAC ADV7123 FEATURES 240 MSPS Throughput Rate Triple 10-Bit D /A Converters SFDR -7 0 dB at f CLK = 50 MHz; f 0 U T = 1 MHz -5 3 dB at f CLK = 1 4 0 MHz; f 0 u i = 40 MHz RS-343A/RS-170 Com patible O utput

SSTL-18

Contextual Info: Stratix GX November 2002, ver. 1.0 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver

SSTL-18

Contextual Info: Using High-Speed Differential I/O Interfaces in Stratix Devices December 2002, ver. 2.0 Introduction Preliminary Information Application Note 202 To achieve high data transfer rates, StratixTM devices support TrueLVDSTM differential I/O interfaces which have dedicated

PC intel 945 MOTHERBOARD CIRCUIT diagram

Abstract: verilog code for cordic algorithm TRANSISTOR SUBSTITUTION DATA BOOK 1993 intel 845 MOTHERBOARD pcb CIRCUIT diagram code for Discreet cosine Transform processor 945 mercury MOTHERBOARD CIRCUIT diagram 484BGA inverter PURE SINE WAVE schematic diagram intel 915 MOTHERBOARD pcb CIRCUIT diagram intel 845 MOTHERBOARD SERVICE MANUAL
Contextual Info: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-3.4 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

PIC16 AD7812

Abstract: AD7811 AD7811YN AD7811YR AD7811YRU AD7812 AD7812YN AD7812YR AD7812YRU N-16
Contextual Info: a 2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs AD7811/AD7812 FEATURES 10-Bit ADC with 2.3 ␮s Conversion Time The AD7811 has Four Single-Ended Inputs that Can Be Configured as Three Pseudo Differential Inputs with Respect to a Common, or as Two Independent Pseudo Differential Channels

A4931

Abstract: tag 8721 IXF1002EC TAG 8822 27831
Contextual Info: IXF1002 Dual Port Gigabit Ethernet Controller Datasheet May 2000 Order Number: 278310-003 Revision History Date Revision Description 8/31/99 001 Initial release. 12/15/99 002 Format revision, electrical specification updates. 5/26/00 003 Updates for IXP1200 v1.0 release.

TLK1201A

Abstract: TLK1221RHAR TLK2201B TLK2201BI TNETE2201
Contextual Info: TLK1221 www.ti.com. SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009 ETHERNET TRANSCEIVER Check for Samples: TLK1221