10K ECL FAMILY Search Results

signal path designer

Contextual Info: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability

6 PIN SMD 3236

Abstract: DM 1265
Contextual Info: M M O T O R O L A Military 10590 Quad MST to M ECL 10K Translator ELECTRICALLY TESTED PER: MPG 10590 The 10590 is a quad translator for interfacing from IBM MST-type logic signals to standard MECL 10K logic levels. This circuit features differential inputs for high

MOTOROLA ECL

Abstract: MC672 REPLACEMENT HTL LOGIC MC667 TRANSISTOR REPLACEMENT GUIDE HTL LOGIC mc660 MC668 mecl10k MHTL MECL III Series
Contextual Info: MECL ECL voltage compensated which allows guaranteed dc and switching parameters over a ± 5 % power supply range. Noise margins of MECL 10KH are 75% better than the MECL 10K series. MECL 10KH is compatible with MECL 10K and MECL III, a key element in allowing users to enhance existing systems by increasing the

Contextual Info: * SYNERGY SY10422-5 SY10422-6 256 x 4 ECL RAM SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The Synergy SY10422 is a 1024-bit Random Access Memory RAM , designed with advanced Emitter Coupled Logic (ECL) circuitry. The SY10422 is organized as 256words-by-4-bits, meets the standard 10K family signal and

Contextual Info: * 16K x 1 ECL RAM SYNERGY SEMICONDUCTOR FEATURES SY10480-6 DESCRIPTION • Address access time, tAA: 6ns max. ■ Chip select access time, tAc: 3ns max. The Synergy SY10480 is a 16384-bit Random Access Memory RAM , designed with advanced Emitter Coupled Logic (ECL) circuitry. The SY10480 is organized as 16384words-by-1-bit, meets the standard 10K family signal and

K1149

Abstract: 50-to-75 RASCO k1519 ECL10KH K1149BA K1149CA K1523BA K1524AA power supply 5v dc
Contextual Info: K1149 Series ECL Compatible Oscillators ECL10KH Based Design - provides im­ proved rise and fall times, duty cycle, noise margins and power supply rejection over the earlier 10K family while retaining compatibil­ ity. Open emitter output allows the user to

LK 1623

Abstract: motorola ECL ELECTRICALLY TESTED 10h536
Contextual Info: M MOTOROLA Military 10H536 Universal Hexadecimal Counter ELECTRICALLY TESTED PER: 5962-870010101 MP0 mini The 10H536 is a high speed synchronous hexadecimal counter. This MECL 10H part which is a functional/pinout duplication of the standard M ECL 10K family

carry look ahead adder

Abstract: Q20010 Q20120 Q20000
Contextual Info: DEVICE SPECIFICATION LOGIC A R R A Y S 020000 Q20000 FEATURES T U R B O ” ECL/TTL Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 100KECL and mixed ECL/TTL capability

Contextual Info: * SYNERGY 256 X 4 ECL RAM SY10422-4 SEMICONDUCTOR Fe a t u r e s • ■ Address access time, tAA :3ns max. d e s c r ip t io n The Synergy SY10422 is a 1024-bit Random Access Memory RAM , designed with advanced Emitter Coupled Logic (ECL) circuitry. The SY10422 is organized as 256words-by-4 bits, meets the standard 10K family signal and

Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet High Performance SLX Family Low Power GaAs Standard Cell Arrays Features • Standard Cell Core • Low-Power Macros Available • Five Array Sizes: 10K, 26K, 48K, 72K and 110K Usable Gates • Standard TTL, LVTTL, ECL, LVPECL, GTL,

Contextual Info: * SY10480-8 SY10480-10 16K x 1 ECLRAM SYNERGY SEM ICO NDUCTO R DESCRIPTION FEATURES The Synergy SY10480 is a 16384-bit Random Access Memory RAM , designed with advanced Emitter Coupled Logic (ECL) circuitry. The SY10480 is organized as 16384words-by-1-bit, meets the standard 10K family signal and

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 2-Input NOR Gate The MC10H102 is a quad 2-input NOR gate. The MC10H102 provides one gate w ith OR/NOR outputs. This M ECL 10H part is a fun ctional/pinout duplication of the standard MECL 10K family part, with 100% improvement in

Contextual Info: MC10H165 MOTOROLA L SU FFIX C ER A M IC PAC KAG E C A SE 620 8-INPUT PRIORITY ENCODER The MC10H165 is an 8-Input Priority Encoder. This 10H part is a functional/pinout duplication of the standard M ECL 10K family part, with 100% improvement in propagation delay, and no

Contextual Info: Clock OsciUMors Pages • • • • TTL CM OS HCMOS/ACMOS/FCT ECL (10K/E/EL, 10 KH, 100K/E/EL, ECLinPS or lite) Sinewave For the moderate stability crystal controlled oscillator where neither temperature compensation nor oven operation are required, there are three primary para­

10H125

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad MECL-to-TTL Translator M C 10H 125 The M C 10H 125 is a quad translator for interfacing data and control signals between the M ECL section and saturated logic section of digital systems. The 10H part is a functional/pinout duplication of the standard M E C L 10K family

311040M

Abstract: VCO-600A od3 tube
Contextual Info: Product Data Sheet VCO-600A Voltage Controlled Saw Oscillator Features • Output Frequency @ 155 MHz to 1 GHz • Low jitter, 1.5pS for 622, 3pS for 155 typical • Ideal for clock smoothing, frequency translation, clock and data retiming applications • 10K ECL, PECL logic levels with fast transition times

Contextual Info: M M O T O R O LA Military 10591 Hex M EC L 10K to MST Translator ELECTRICALLY TESTED PER: MPG 10591 The 10591 is a hex M ECL to IBM M ST type logic translator. A common enable (active low) is provided for gating. Open emitter outputs are provided for gating.

SE648

Abstract: SE775
Contextual Info: M OTOROLA L SUFFIX C ER A M IC PACKAG E C A S E 620 DUAL 4-5-INPUT "OR/NOR" GATE The MC10H109 is a dual 4-5-input OR/NOR gate. This M ECL 10H part is a functional/pinout duplication of the standard M EC L 10K family part, with 100% improvement in propagation delay, and

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple 2-3-2-Input OR/NOR Gate The M C 10H 105 is a triple 2 -3 -2 -in p u t O R /N O R gate. This M ECL 10H part is a functional/pinout duplication of the standard M EC L 10K family part, with 100% improvement in propagation delay, and no increases in power-supply

MC10131

Abstract: 10H131 mc10h131 MC-10131
Contextual Info: ECL 10K H H igh-S peed E m itter-C oupled Logic F am ily M C 10H 131 Dual M aster-S lave Type D F lip -F lo p F e a tu re s / Benefits Ordering Inform ation • Propagation delay, 1 ns typical PART NUMBER PACKAGE TEMPERATURE MC10H131 J,N,NL 20 Com • Power dissipation, 235 mW typical

LCA10075

Abstract: LMA9000 lca10129 LCA10000 LCA10051
Contextual Info: NOV 0 5 LSI LOGIC 19M LCA10000 Compacted Array Series Description The LCA10000 Com pacted A rra y se rie s is an HCMOS sem icustom te c h n o lo g y o ffe rin g speed pe rfo rm a n ce e q u iv a le n t to 10K ECL, com bined w ith ve ry high gate counts. The LCA10000

LMA9000

Abstract: LMA9190 a9284 LMA9050 A9072 tc 74181 alu A9033
Contextual Info: LSI LOGIC . 1390 LMA9000 M icro Array Series Description The LMA9000 M ic ro A rra y se rie s is an HCMOS se m icu sto m te c h n o lo g y o ffe rin g both speed and pe rfo rm a n ce e q u iva le n t to 10K ECL and high gate d e n sity ASICs. The LMA9000 M ic ro

MECL III Series

Abstract: MC12000
Contextual Info: HIGH–SPEED LOGIC increasing the speed in critical timing areas. Also, many MECL 10H devices are pin out/functional duplications of the MECL 10K series devices. The emphasis of this family will be placed on more powerful logic functions having more complexity and greater performance. With 1.0 ns