10KRESISTOR NET Search Results

A1010-PL

Abstract: Microsoft 007 ird
Contextual Info: ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates

172CQFP

Abstract: A1225 A1225A A1240 A1240A A1280 A1280A actel a1280a unused pin SV50T actel a1240
Contextual Info: ém cM ACT“ 2 Family FPGAs Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages Two In-Circuit Diagnostic Probe Pins Support Speed

Contextual Info: RadHard Field Programmable Gate Arrays Features P ro d u c t F am ily P rofile • Guaranteed Total Dose Radiation Capabilit Device • Low Single Event Upset Susceptibility RH1020 RH1280 Capacity • High Dose Rate Survivability 2 ,0 0 0 8 ,0 00 6 ,0 0 0

rd8 f01 ad

Abstract: MOCK
Contextual Info: Æ k ù iil Accelerator Series FPGAs ACT 3 PCI-Compliant Family • HI m*S M F e a tu re s • Up to 10,000 Gate Array Equivalent Gates. • Highly Predictable, Synthesis-Friendly Architecture Supports High-Level Design Methodologies. . Up to 250 MHz On-Chip Performance.

RD212

Abstract: A1415 A1425 A1425A-3 A1440 A1460 actcl AH25A-3
Contextual Info: Accelerator Series FPGAs - ACT 3 Family Features Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates Replaces up to one hundred 20-pin PAL Packages Up to 1153 Dedicated Flip-Flops

5962-9096504MTA

Contextual Info: Military Field Programmable Gate Arrays Features A C T 3 Features Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family Device Sizes from 1200 to 10,000 gates up to 25,000 PLD

RT1280A-CQ172E

Abstract: RT1280A-CQ172 RT1280A
Contextual Info: RadTolerant Field Programmable Gate Arrays F e a tu re s • Secure Programming Technology Engineering and Design Theft G e n e r a l C h a r a c te r is t ic s Prevents Reverse • Permanently Programmed for Instantaneous Operation on Power-Up • Tested Total Ionizing Dose TID Survivability Level

A1010B

Abstract: A1020B A1010 A1020 DN241 actel a1020b actel a10v20b ACTEL A1010 LL HP A1010-PL
Contextual Info: Æ 9 c t§ Ê • ACT 1 Series FPGAs Features A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. P ro d u c t F a m ily P ro file • Replaces up to 50 TTL Packages A 1010B

spw 068

Contextual Info: Accelerator Series FPGAs - ACT 3 Family F e a tu re s • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates • Replaces up to one hundred 20-pin PAL Packages • Highly Predictable Performance with 100% Automatic

78f1213

Abstract: flash programmer minicube2 schematic minicube2 circuit schematic 2SB22 HC49US uPD78K0R-IC3 three phase bldc motor drive schematic hex code uPD78F1213 3 terminal mosfet p51 PITTMAN encoder
Contextual Info: User's Manual MC-CPU-78K0RIC3 CPU Daughter Card For use with the Low Voltage Motor Control Starter Kit Document No. U19825EE1V0UM00 Date published June 2009 NEC Electronics 2009 Printed in Germany Legal Notes 2 • The information in this document is current as of May, 2008. The

Contextual Info: ACT 2 Family FPGAs F e a tu re s • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages Two In-Circuit Diagnostic Probe Pins Support Speed

uPD78K0R-IE3

Abstract: flash programmer minicube2 schematic 2SB22 74AHC1G125DBVR HC49US map diagram RPM meter MC-LVKIT-714 mc 741 PITTMAN encoder TI07
Contextual Info: User's Manual MC-CPU-78K0RIE3 CPU Daughter Card For use with the Low Voltage Motor Control Starter Kit Document No. U19824EE1V0UM00 Date published June 2009 NEC Electronics 2009 Printed in Germany Legal Notes 2 • The information in this document is current as of May, 2008. The

SiS 486 schematic

Contextual Info: Accelerator Series FPGAs - ACT 3 Family Features • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent P L IJ Gates • Replaces up to one hundred 20-pin PAL Packages • Highly Predictable Performance with 100% Automatic

132-PIN CERAMIC PIN GRID ARRAY CPGA

Abstract: A1280A-PG176B 32200D smd transistor JJ
Contextual Info: = * 4 c t e ml HiRel FPGAs Features 3200DX • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • 100 MHz System Logic Integration • Device Sizes from 1200 to 20,000 gates • Highest Speed FPGA SRAM, up to 2.5 Kbits Configurable

RTM 866 - 480

Abstract: saj 141 OA67 wd 969 ir 40MX04 RTM 866 - 485 kSO 947 262
Contextual Info: 40 Preliminary D ala Sheet -» Revision 1.1 I ntegr ator SeriesFP GAs: 40MX and 42MX Families Features * Deterministic, User-Controllable Timing Via DirectTime Software Tools. High C apacity * MX Diagnostics and Debug Supported by Silicon Explorer. * 2,000 to 52,000 Available Logic Gates

A42MXI6

Abstract: 1043U 144-40M SKM 181 c ST 1803 DHL 47-16 RD2 diode
Contextual Info: ^ c t e•"—TPl v3.0 40MX and 42MX Families FPGAs F e a tu re s • QML Certification H ig h C a p a c ity • Ceramic Devices Available to DSCC SMD • Single Chip ASIC Alternative E a s e o f In te g r a tio n • 2,000 to 36,000 Available Logic Gates