112SD Search Results

Contextual Info: LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 LMV112 40 MHz Dual Clock Buffer Check for Samples: LMV112 FEATURES DESCRIPTION • The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two

Contextual Info: LMV112 LMV112 40 MHz Dual Clock Buffer Literature Number: SNAS297A LMV112 40 MHz Dual Clock Buffer General Description Features The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two 40 MHz low noise buffers which

LMV112

Abstract: LMV112SD LMV112SDX SDA08A
Contextual Info: LMV112 40 MHz Dual Clock Buffer General Description Features The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two 40 MHz low noise buffers which optimizes application and out performs large discrete solutions. This device enables superb system operation between

TRANSISTOR k2185

Contextual Info: Model 540 Voltsensor CALEX MANUFACTURING CO SEE 2401 Stanwell Drive, Concord, CA 94520-4841 D 1011250 000105b 510 687-4411 (800)542-3355 37b « C E X FAX: (510) 687-3333 FEATURES • Rugged reliable solid state replacement for meter relays. • Uses almost any power source from +5 to +32V D C

Contextual Info: LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 LMV112 40 MHz Dual Clock Buffer Check for Samples: LMV112 FEATURES DESCRIPTION • The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two

WD33C96A

Abstract: TGS 815 WD42C22
Contextual Info: ‘ . ^ ^TORAGE WESTERN DIGITAL CORP .* • j •- I SME D ■ R716SS6 0D15H2Û ‘ÌOS * U P C " T 'S 2 - 3 3 - Z 7 ■• ' * - ! ' *.• I .' I W D33C95A, W D33C96A w m m m sim m m m . E nhanced Single-ended an d Differential SC SI Bus Interface Controller

90C24LC

Abstract: CNF17 amd1018 algorithm draw line graphic programing BMD5 bt ramdac vl-bus STN11 cga ega vga TFT Display controller 90C24
Contextual Info: 90C24LC 1.0 INTRODUCTION 1.1 GENERAL DESCRIPTION INTRODUCTION This document describes the Philips Semiconduc­ tors 90C24LC Windows Accelerated High Resolu­ tion VGA LCD Controller for Low Power Applications hereinafter referred to as the 90C24LC Controller .

Contextual Info: LMV112 LMV112 40 MHz Dual Clock Buffer Literature Number: SNAS297A LMV112 40 MHz Dual Clock Buffer General Description Features The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two 40 MHz low noise buffers which

Contextual Info: LMV112 www.ti.com SNAS297A – JUNE 2005 – REVISED JULY 2005 LMV112 40 MHz Dual Clock Buffer Check for Samples: LMV112 FEATURES 1 • 2 • • • • • • • • • • • Typical Values are: VSUPPLY = 2.7V and CL = 20 pF, Unless Otherwise Specified.

SNAS297B

Contextual Info: LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 LMV112 40 MHz Dual Clock Buffer Check for Samples: LMV112 FEATURES DESCRIPTION • The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two

Contextual Info: LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 LMV112 40 MHz Dual Clock Buffer Check for Samples: LMV112 FEATURES DESCRIPTION • The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two

WD33C93A

Abstract: WD33C93 da 8012 muic 93-SD140E microprocessor ic 501 WD33C95A WD33C96A 80c196 63-BDPL
Contextual Info: INTRODUCTION d WESTERN DIGITAL CORP 1.0 INTRODUCTION ' • ♦ ‘ S’ ; ’ In this document, the term ESBC Enhanced SCSI bus controller is used as a term when refer­ ring to both parts. The ESBC can perform both as an Initiator and target. The data path for this deyice is program*

WD33C96A

Abstract: 33-SDOOE 80C196 mnemonic C40A 80C196 WD33C92A WD33C95A WD61C40A 62-DRQB 21mux
Contextual Info: WD33C95A/WD33C96A INTRODUCTION 1.0 INTRODUCTION 1.1 DOCUMENT SCOPE 1.3 This document describes two versions of a single chip VLSI SCSI bus controller. The WD33C96A is a 100-pin device that can act only as a single­ ended SCSI controller, and the WD33C95A is a