130TH Search Results

TSL202

Abstract: TAOS032 TSL202R
Contextual Info: TSL202R 128 y 1 LINEAR SENSOR ARRAY t t TAOS032 – SEPTEMBER 2001 D 128 x 1 Sensor-Element Organization D 200 Dots-Per-Inch DPI Sensor Pitch D High Linearity and Uniformity (TOP VIEW) VDD SI1 CLK AO1 GND SO2 VDD for 256 Gray-Scale (8-Bit) Applications

Contextual Info: TSL1401 128 x 1 LINEAR SENSOR ARRAY WITH HOLD t t TAOS001A – MAY 1999 D 128 × 1 Sensor-Element Organization D 400 Dots-Per-Inch DPI Sensor Pitch D High Linearity and Uniformity (TOP VIEW) SI CLK AO VDD for 256 Gray-Scale (8-Bit) Applications Output Referenced to Ground

Contextual Info: CMOS DUAL SyncFlFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18 FEATURES: • The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs • The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs • The IDT72825LB is equivalent to two IDT72225LB 1,024 x 18

Motorola MC6805 pin diagram

Abstract: MC6805 motorola a00a a06b 848B AN1066 AN442 MC145003 MC145004 MC6805
Contextual Info: MOTOROLA Order this document by MC145003/D SEMICONDUCTOR TECHNICAL DATA MC145003 MC145004 Product Preview 128 Segment LCD Drivers CMOS 1 ORDERING INFORMATION MC145003FU MC145004FU QFP QFP PIN ASSIGNMENT FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22

SH72533

Abstract: R5F72533KFPU
Contextual Info: User's Manual The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH72533 32 User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family SH72533 R5F72533KFPU

IDT72205LB

Abstract: IDT72215LB IDT72225LB IDT72235LB IDT72245LB IDT72805LB IDT72815LB IDT72825LB IDT72835LB IDT72845LB
Contextual Info: PRELIMINARY IDT72805LB IDT72815LB IDT72825LB IDT72835LB IDT72845LB CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18 FEATURES: • • • • • • The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs

Transfer Clock in FWFT

Contextual Info: AL4CS205 AL4CS215 AL4CS225 AL4CS235 AL4CS245 Data Sheets Version 2.1 AL4CS205/AL4CS215/AL4CS225/AL4CS235/AL4CS245 Amendments 7.10.01 Preliminary version 1.0 10.17.01 Version 1.1, Add DC and AC timing data 11.28.01 Version 1.2, modify 8.5 programmable timing selection

QA-12

Contextual Info: CMOS DUAL SyncFlFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18 FEATURES: • The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs • The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs • The IDT72825LB is equivalent to two IDT72225LB

1277H

Abstract: 72V205
Contextual Info: 3.3 VOLT CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72V205, IDT72V215, IDT72V225, IDT72V235, IDT72V245 FEATURES: DESCRIPTION: • • • • • • The IDT72V205/72V215/72V225/72V235/72V245 are functionally compatible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,

IDT72205LB

Abstract: IDT72215LB IDT72225LB IDT72235LB IDT72245LB IDT72805LB IDT72815LB IDT72825LB IDT72835LB IDT72845LB
Contextual Info: IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL TEMPERATURE RANGES CMOS DUAL SyncFIFO™ DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

2V205

Contextual Info: 3.3 VOLT CMOS SyncFIFO 2 5 6 x 1 8 ,5 1 2 x 1 8 ,1 ,0 2 4 x 1 8 , 2,048x18 and 4,096x18 FEATURES: • • • • • • • • • • • • • • • • • 256 x 18-bit organization array IDT72V205 512 x 18-bit organization array (IDT72V215)

Contextual Info: PR ELIM IN A R Y IDT72805LB IDT72815LB IDT72825LB IDT72835LB IDT72845LB CMOS DUAL SyncFlFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096x18 FEATURES: • IDT Standard or First Word Fall Through timing • The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs

5003s

Abstract: AN1066 MC145003 MC145004 MC14LC5002 MC14LC5003 MC14LC5004 MC68HCXX Motorola 2.8 LCD Technical Data
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14LC5002 MC14LC5003 MC14LC5004 72-Segment / 128-Segment LCD Drivers QFP FU SUFFIX CASE 848B TQFP FB SUFFIX CASE 873A CMOS The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Drivers. The MC14LC5002 is the same as MC14LC5003 except for 72 segments.

MC14LC5003AFU

Abstract: MC14LC5003A FP31F fp1 fp2 fp3
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14LC5002A MC14LC5003A MC14LC5004A Product Preview 72-Segment / 128-Segment LCD Drivers QFP FU SUFFIX CASE 848B TQFP FB SUFFIX CASE 873A CMOS The MC14LC5003A/5004A are 128-segment, multiplexed-by-four LCD Drivers. The MC14LC5002A is the same as MC14LC5003A except for 72

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14LC5002 MC14LC5003 MC14LC5004 72-Segment / 128-Segment LCD Drivers QFP FU SUFFIX CASE 848B TQFP FB SUFFIX CASE 873A CMOS The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Drivers. The MC14LC5002 is the same as MC14LC5003 except for 72 segments.

lcd pm 128 bl

Abstract: lcd 1110 a04e Y545 848B-02 6 pin mini din lcd MC14LC5003A 542B0
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14LC5003 MC14LC5004 128 Segm ent LCD Drivers CMOS The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Driv­ ers. The two devices are functionally the same except for their data input protocols. The MC14LC5003 uses a serial interface data input protocol. The

TSL202

Abstract: TSL202R
Contextual Info: TSL202R 128 y 1 LINEAR SENSOR ARRAY r r D D D D D D D D D TAOS032D − APRIL 2009 128 x 1 Sensor-Element Organization 200 Dots-Per-Inch DPI Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 2000:1 (66 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ

Contextual Info: IDT72V805 IDT72V815 IDT72V825 IDT72V835 IDT72V845 3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18 FEATURES: • • • • • • • • • • • The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs

R5F72543

Abstract: SH72544 sh72543 R5F72544 FAAC 826 98.0 SH72544R H11F 5-pin R5F72543RKBGV R5F72544RKBGV Renesas SH72543R
Contextual Info: User's Manual The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7254R Group 32 User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family

PW01

Abstract: MS3119 MS3114 PW02 MIL-C-26482 connector MS3119 PW08
Contextual Info: Array PW Series PW00/MS3110 Wall Mount Receptacle PW01/MS3111 In-Line Receptacle Solder/Bayonet Coupling Connectors MIL-C-26482, Series I Commercial and Military QPL’d Array Connector Corporation manufactures an extensive line of Bayonet Coupling Connectors

pll fm demodulator

Abstract: schematic diagram SCPC dm565 C337 725 mtld DS5347 Single Chip zero IF L-band Tuner DVB Satellite LK-19 Tuner ts pinout viterbi algorithm
Contextual Info: MT312 Satellite Channel Decoder Design Manual Supersedes DS5347 Issue 1.2 November 2001 DM5651 Key Features • • • • • • • • • • • • • • • January 2002 Ordering Information MT312C/CG/GP1N Conforms to EBU specification for DVB-S and

transmitter qpsk schematic diagram

Abstract: receiver qpsk schematic diagram diseqc DiSEqC 1.0 / 1.1 1/3 Convolutional encoder demodulator qpsk qpsk transmitter phase accumulator with bpsk CT-102 low cost qpsk modulator
Contextual Info: MT312 Satellite Channel Decoder Design Manual Part Number: MT312 Issue Date: August 2003 This page intentionally left blank. MT312 Design Manual Table of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

AK8854VQ

Abstract: SMPTE-253M AK8854 bt.656 interface burst signal
Contextual Info: [AK8854VQ] AK8854VQ Multi-Format Digital Video Decoder Overview The AK8854VQ is a single-chip digital video decoder for composite, s-video, component YPbPr and RGB video signals. In case of RGB, AK8854VQ support Sync on Green,CSYNC and H/VSYNC as sync signal. Its output data is in YCbCr format, compliant with ITU-R BT.601. Its pixel clock, with a

IDT72V205

Abstract: IDT72V215 IDT72V225 IDT72V235 IDT72V245 72V205
Contextual Info: IDT72V205 IDT72V215 IDT72V225 IDT72V235 IDT72V245 3.3 VOLT CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 FEATURES: • • • • • • • • • • • • • • • • • These devices are very high-speed, low-power First-In, First-Out FIFO