15ELECTRONICS Search Results

Contextual Info: KM718V895 256Kx18 Synchronous SRAM Document Title 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0 .0 Initial d ra ft F e bru ary. 02. 1998 P re lim in a ry 0.1 C h a n g e DC c h a ra c te ris tic s V dd c o n d itio n fro m V d d = 3 .3 V + 1 0 % /-5 % C h a n g e

Contextual Info: KM736V795 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 In itia l d r a ft February. 02. 1 9 9 8 Prelim inary 0.1 Change DC characteristics V d d condition from V d d = 3 .3 V + 1 0 % /- 5 % Change

Contextual Info: KM718V889 256Kx18 Synchronous SRAM Document Title 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. Historv Draft Date REMARK 0.0 Initial draft May . 15. 1997 Prelim inary 0.1 Change 7.5 bin to 7.2 January . 13 . 1998 Prelim inary 0.2

Contextual Info: KM736V849 KM718V949 PRELIMINARY 256Kx36 & 512KX18 Pipelined NfRAM Document Title 256Kx36 & 512Kx18-Bit Pipelined NfRAM™ Revision History Rev. No. 0.0 History 1. Initial document. Draft Date Remark June. 09. 1998 Preliminary 0.1 1. Changed DC parameters

Contextual Info: KM736S849 KM718S949 PRELIMINARY 256Kx36 & 512Kx18 Pipelined NfRAM Document Title 256KX36 & 512Kx18-Bit Pipelined NfRAM™ Revision History Rev. No. Historv Draft Date Remark 0.0 1. Initial document. September. 1997 Prelim inary 0.1 1. Changed speed bin from 167MHz to 150MHz

Contextual Info: KM736V890 KM718V990 PRELIMINARY 256Kx36 & 512Kx18 Synchronous SRAM 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Rev. No. History Draft Date Remark 0.0 Initial draft May. 07 . 1998 Preliminary 0.1 Modify DC characteristics Input Leakage Current test Conditions

Contextual Info: KM736V790 128Kx36 Synchronous SRAM Document Tills 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft December. 15. 1997 Prelim inary 0.1 Change speed symbol 6.0/6.7/7.5/8.5 to 60/67/75/85, Change 7.5 bin to 7.2

Contextual Info: KM718V895 256Kx18 Synchronous SRAM Document Title 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft F e bru ary. 02. 1998 P re lim in a ry 0.1 C h a n g e D C c h a ra c te ris tic s V dd c o n d itio n fro m V dd = 3 .3 V + 1 0 % /-5 % C h a n g e

KM48S2020A

Abstract: km48s2020at K/A8-A10 050S53 1994 sdram 002G5 D02g DD2054 samsung AND 1994 AND sdram
Contextual Info: PRELIMINARY * KM48S2020A CMOS SDRAM 2M X 8 BIT SYNCHRONOUS DYNAMIC RAM GENERAL DESCRIPTION FEA TU RES - JED EC standard 3.3V power supply. - LVTTL compatible with multiplexed address. - Dual bank / Pulse RAS. - W CBR cycle with address key programs. •Latency Access from column address

Contextual Info: KM732V789 128Kx32 Synchronous SRAM Document Title 128Kx32-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 1.0 Initial draft M a y. 1 9 .1 9 9 8 Final 2.0 change tCYC from 8.5ns to 10.0ns. M odify Rev No. from 0.0 to 1.0.