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    165 BALL FBGA Search Results

    165 BALL FBGA Result Highlights (1)

    Part ECAD Model Manufacturer Description Download Buy
    CYD18S36V18-167BBAI
    		Rochester Electronics LLC 512KX36 DUAL-PORT SRAM, 4ns, PBGA256, 17 X 17 MM, 1.70 MM HEIGHT, 1 MM PITCH, MO-192, FBGA-256 Visit Rochester Electronics LLC

    165 BALL FBGA Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    BB209

    Abstract: BB100 BB484 165 BALL FBGA BB42 bb209a 288-ball 676-BALL BB165B
    Contextual Info: Package Diagrams Thin Ball Grid Array Packages 42-Ball Thin Ball Grid Array 6 x 5 x 1.2 mm BB42 51-85139-*A 1 Package Diagrams 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107-*B 2 Package Diagrams 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A 51-85122-*B


    Original     		42-Ball 100-Ball BB100 165-Ball BB165A BB165B BB165C 172-Ball BB209 BB100 BB484 165 BALL FBGA BB42 bb209a 288-ball 676-BALL BB165B PDF

    100-Ball

    Abstract: 288-ball
    Contextual Info: Package Diagrams Thin Ball Grid Array Packages 100-Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85107 1 Package Diagrams 165-Ball FBGA (13 x 15 x 1.35 mm) BB165 51-85122 2 Package Diagrams 172-Ball FBGA BB172 51-85114 3 Package Diagrams 256-Ball Thin Ball Grid Array (17 x 17 mm) BB256


    Original     		100-Ball BB100 165-Ball BB165 172-Ball BB172 256-Ball BB256 1-85108-A 288-Ball PDF

    G38-87

    Abstract: MT54V1MH18A MT54V512H36A
    Contextual Info: 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, QDRb2 SRAM 18Mb QDR SRAM 2-Word Burst MT54V1MH18A MT54V512H36A FEATURES 165-BALL FBGA • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation


    Original     		MT54V1MH18A MT54V512H36A 165-BALL MT54V1MH18A G38-87 MT54V512H36A PDF

    Contextual Info: 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, QDRb2 SRAM 18Mb QDR SRAM 2-WORD BURST MT54V1MH18A MT54V512H36A Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE


    Original     		MT54V1MH18A PDF

    Contextual Info: 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-BALL FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation


    Original     		MT54V512H18A 165-BALL MT54V512H18A PDF

    micron sram

    Abstract: G38-87 MT54V1MH18A MT54V512H36A
    Contextual Info: 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, QDRb2 SRAM 18Mb QDR SRAM 2-WORD BURST MT54V1MH18A MT54V512H36A Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE


    Original     		MT54V1MH18A MT54V512H36A 165-Ball MT54V1MH18A micron sram G38-87 MT54V512H36A PDF

    MT54W1MH18B

    Abstract: MT54W2MH8B MT54W512H36B G38-87
    Contextual Info: 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, QDRIIb2 SRAM 18Mb QDR II SRAM 2-WORD BURST MT54W2MH8B MT54W1MH18B MT54W512H36B Features Figure 1: 165-Ball FBGA • DLL circuitry for accurate output data placement • Separate independent read and write data ports with


    Original     		MT54W2MH8B MT54W1MH18B MT54W512H36B 165-Ball MT54W1MH18B MT54W2MH8B MT54W512H36B G38-87 PDF

    Contextual Info: ADVANCE‡ 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, QDRb2 SRAM 18Mb QDR SRAM 2-Word Burst MT54V1MH18A MT54V512H36A FEATURES 165-BALL FBGA • 18Mb Density • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE


    Original     		MT54V1MH18A MT54V512H36A 165-BALL MT54V1MH18A PDF

    Contextual Info: 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Ball FBGA Fast cycle times: 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation


    Original     		MT57V256H36P 165-Ball MT57V256H36P PDF

    MT57V256H36P

    Contextual Info: 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Ball FBGA Fast cycle times: 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation


    Original     		MT57V256H36P 165-Ball MT57V256H36P PDF

    Contextual Info: PRELIMINARY‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, QDRIIb2 SRAM 18Mb QDR II SRAM 2-WORD BURST MT54W2MH8B MT54W1MH18B MT54W512H36B Features Figure 1: 165-Ball FBGA • DLL circuitry for accurate output data placement • Separate independent read and write data ports with


    Original     		PDF

    Contextual Info: 1 MEG x 18, 512 x 36 2.5V VDD, HSTL, PIPELINED DDRb2 SRAM 18Mb DDR SRAM 2-Word Burst MT57V1MH18A MT57V512H36A Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times Pipelined, double data rate operation


    Original     		MT57V1MH18A PDF

    4p toggle switch

    Abstract: MARKING CCK MARKING CODE 9N micron sram MT57V1MH18A MT57V512H36A
    Contextual Info: 1 MEG x 18, 512 x 36 2.5V VDD, HSTL, PIPELINED DDRb2 SRAM 18Mb DDR SRAM 2-Word Burst MT57V1MH18A MT57V512H36A Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times Pipelined, double data rate operation


    Original     		MT57V1MH18A MT57V512H36A 165-Ball MT57V1MH18A 4p toggle switch MARKING CCK MARKING CODE 9N micron sram MT57V512H36A PDF

    Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb2 SRAM 36Mb QDR SRAM 2-WORD BURST MT54V2MH18A MT54V1MH36A Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE


    Original     		MT54V2MH18A PDF

    Contextual Info: 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM 18Mb DDR SRAM 4-Word Burst MT57V1MH18E MT57V512H36E Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times Pipelined, double data rate operation


    Original     		MT57V1MH18E PDF

    HSTL standards

    Abstract: micron sram
    Contextual Info: ADVANCE‡ 0.16µm Process 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36E FEATURES • • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times: 5ns and 6ns 256K x 36 configuration


    Original     		MT57V256H36E 165-Ball MT57V256H36E HSTL standards micron sram PDF

    Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb4 SRAM 36Mb QDR SRAM 4-WORD BURST MT54V2MH18E MT54V1MH36E Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE


    Original     		MT54V2MH18E PDF

    Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb2 SRAM 36Mb QDR SRAM 2-WORD BURST MT54V2MH18A MT54V1MH36A Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE


    Original     		MT54V2MH18A PDF

    MARKING CCK

    Abstract: micron sram MT57V1MH18E MT57V512H36E
    Contextual Info: 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM 18Mb DDR SRAM 4-Word Burst MT57V1MH18E MT57V512H36E Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times Pipelined, double data rate operation


    Original     		MT57V1MH18E MT57V512H36E 165-Ball MT57V1MH18E MARKING CCK micron sram MT57V512H36E PDF

    Contextual Info: ADVANCE‡ 0.16µm Process 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36E FEATURES • • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times: 5ns and 6ns 256K x 36 configuration


    Original     		MT57V256H36E PDF

    Contextual Info: ADVANCE‡ 0.16µm Process 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM 4-WORD BURST MT54V512H18E Features Figure 1: 165-Ball FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE


    Original     		MT54V512H18E PDF

    Contextual Info: ADVANCE‡ 0.16µm Process 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM 2-WORD BURST MT54V512H18A Features Figure 1: 165-Ball FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE


    Original     		MT54V512H18A PDF

    Contextual Info: ADVANCE‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, QDRIIb4 SRAM 18Mb QDR II SRAM 4-Word Burst MT54W2MH8J MT54W1MH18J MT54W512H36J FEATURES 165-BALL FBGA • 18Mb Density 2 Meg x 8, 1 Meg x 18, 512K x 36 • DLL circuitry for wide-output, data valid window


    Original     		MT54W1MH18J PDF

    Contextual Info: ADVANCE‡ 2 MEG x 8, 1 MEG x 18, 512K x 36 1.8V VDD, HSTL, QDRIIb4 SRAM 18Mb QDR II SRAM 4-Word Burst MT54W2MH8J MT54W1MH18J MT54W512H36J FEATURES 165-BALL FBGA • 18Mb Density 2 Meg x 8, 1 Meg x 18, 512K x 36 • DLL circuitry for wide-output, data valid window


    Original     		MT54W1MH18J PDF