16KX64 Search Results

CL018G

Abstract: M1T1HT18PL64E 16Kx64 M1T1HT18PL32E fast sram 100mhz mosys sram embedded
Contextual Info: High Speed Pipelined 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PL64E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late write mode timing • 64-Bit wide data buses

CL018G

Abstract: M1T1HT18PE64E Signal Technology 16Kx64
Contextual Info: High Speed Pipelined 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PE64E • High Speed 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Early write mode timing • 64-Bit wide data buses

CL018G

Abstract: M1T1HT18FL64E MoSys MoSys sram embedded
Contextual Info: High Speed Flow-through 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT18FL64E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 64-Bit wide data buses

TSMC 0.25Um

Abstract: MOSYS M1T1HT25PZ32 M1T1HT25PZ64
Contextual Info: High Speed Pipelined 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT25PZ64 • High Speed 1T-SRAM Standard Macro • 166 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 64-Bit wide data buses

M1T1HT25FL64

Contextual Info: High Speed Flow-through 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT25FL64 • High Speed 1T-SRAM Standard Macro • 83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 64-Bit wide data buses

M1T1LT18FL64E

Abstract: CL018G M1T1LT18FL32E MoSys
Contextual Info: Low Power Flow-through 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1LT18FL64E • Low Power 1T-SRAM Standard Macro • 10-83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 64-Bit wide data buses

TSMC 0.18um

Abstract: CL018G M1T1LT18FE64E tsmc sram
Contextual Info: Low Power Flow-through 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1LT18FE64E • Low Power 1T-SRAM Standard Macro • 10-83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 64-Bit wide data buses

CL018G

Abstract: tsmc sram TSMC 0.18um SRAM TSMC 0.18um Process parameters M1T1HT18PL64E M1T1HT18PZ64E MoSys sram embedded MoSys 1T sram tsmc 0.18um
Contextual Info: High Speed Pipelined 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PZ64E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 64-Bit wide data buses

1MD45

Abstract: cy17 High-Zt11-12 CY10 CY82C691 CY82C692 CY82C693 DQ23P cy82
Contextual Info: PRELIM INARY CY82C692 W CYPRESS Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence

NM6404

Abstract: 9698
Contextual Info: RESEARCH CENTER NeuroMatrix NM6404 DSP NeuroMatrix ® NM6404 is a high performance DSP oriented RISC processor designed for real time data flow processing. The architecture is based on advanced VLIW/SIMD NMC2 core and includes two main units: 32/64-bit RISC and patented

Contextual Info: PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path/Integrated Cache for h C -VX, h C -D X Solutions Features Two-bit wraparound counter supporting Intel Burst or Linear burst sequence Supports 3-1-1-1 Level 2 cache operation up to 66 MHz bus speed

692CU

Abstract: 82c pci isa
Contextual Info: PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • O n -C h ip 8-D ee p F IF O s s u p p o rt P o st-W ritin g /P re-R e ad ing PCI data • S u p p o rts all 3.3 V P e n tiu m ™ -c la s s p ro ces so rs , A M D

D1159

Abstract: ds 157
Contextual Info: PRELIMINARY CYM74B430 CYM74P430/31 CYM74S430/31 Intel 82430FX PCIset Level II Cache Module Family Features * 33V compatible inputs/data outputs • Pin-compatible secondary cache module family that adheres to the Intel COAST 1.1 specification • Asynchronous CYM74B430 , syn­

82430FX

Abstract: CYM74B430 CYM74P430 CYM74P431 CYM74S430 CYM74S431 P54C ZENER A18 Burndy 75 74s430
Contextual Info: PRELIMINARY CYM74B430 CYM74P430/31 CYM74S430/31 Intel 82430FX PCIset Level II Cache Module Family Features D D Functional Description D PinĆcompatible secondary cache modĆ ule family that adheres to the Intel COAST 1.1 specification Ideal for Intel® P54CĆbased systems

at8989p

Abstract: 9-Port Fast Ethernet Repeater ATAN TECHNOLOGY TTL 7490 AT8989UP Tx/Fx Media Converter 400M 9-Port Fast Ethernet Switch serial parallel decoder nrzi circuit diagram MLT-3
Contextual Info: ATAN Technology, Inc. AT8989UP 9 port 10/100 Mb/s Single Chip Ethernet Switch Controller Preliminary Data Sheet Revision 1.1 Feb 2002 Revision 1.1 AT8989UP 9 port 10/100Mb/s Single Chip Switch Controller 1 ATAN Technology, Inc. Revision History Revision Date

PM-66C

Abstract: TIC 2460 82340 82430FX CYM74B430 CYM74P430 CYM74P431 CYM74S430 CYM74S431 74P431
Contextual Info: ^ S -;= i a g T n u n n rn r y L - Ï i PRELIMINARY n Lob = Intel 82340FX PCIset Level II Cache Module Family Features • Pin-compatible secondary cache m odulefam ily that ad­ heres to the Intel COAST 1.1 specification • Asynchronous CYM74B430 , synchronous pipelined

82c691

Abstract: m040 m043 M046 CY10 CY2254ASC-2 CY27C010 CY82C691 CY82C693 cy82
Contextual Info: p - : : : îW j r y n n I? Q c I 1 i l l l D D PRELIMINARY CY82C690 Pentium hyperCache™ Chipset Data-Path/lntegrated Cache for hC-ZX Solution Features • Supports all 3.3V Pentium™ -class processors, AMD K5, and Cyrix M1 CPUs • Directly interfaces with CY82C691 and CY82C693 to

A5 GNC

Abstract: A1W 73 c877 A64A A1 GNC cym74sp55pm 82430NX CYM74BP54 CYM74P54 0/mosfet A5 GNC
Contextual Info: CYM74BP54 CYM74P54/55 CYM74SP54/55 æ r~ ^ S T •= • > y PRELIMINARY n u n n rn r L- Ï i n L o b = Intel 82430NX Chipset Level II Cache Module Family Features • Pin-compatible secondary cache module fam ily • Asynchronous CYM74BP54 , synchronous pipelined

ADU01

Abstract: Intel P55 Chipset D31CD
Contextual Info: — ^ C Y M 7 4 B P 5 4 CYM 74P54/55 ^ l r t î m n r n P R E L IM IN A R Y . n wm W U ir K fc b b C Y M 7 4 S P 5 4 /5 5 — Intel 82430NX Chipset Level II Cache Module Family Feat ures • Pi n- compat i bl e secondary cache mo d ul e family • As yn ch r o no u s CYM7 4BP5 4 , sync h r o no us pipelined

NM6405

Abstract: AMBA AXI ARM1176JZF-S NM6403 NM6404 ARM11 ARM1176 ARM1176 processor
Contextual Info: УДК 004.383.4 Система на кристалле 1879ХК1 для цифровой обработки аналоговых сигналов в радиотехнических системах и спутниковой навигации Д.Е. Косоруков, А.Л. Эйсымонт, В.Г. Осипов, А.П. Панфилов,

74P55

Abstract: LA17-LA5
Contextual Info: 1CY M74 SP5 4/55 CYM74BP54 CYM74P54/55 CYM74SP54/55 PRELIMINARY Intel 82430NX Chipset Level II Cache Module Family Features dustry standard 5V SRAMs and 3.3V level translators for CPU bus speeds up to 66 MHz. The CYM74BP54 is organized as 32K by 64-bits.

Contextual Info: CYPRESS CYM74BP54 CYM74P54/55 CYM74SP54/55 PRELIMINARY Features • Pin-compatible secondary cache m odule fam ily • Asynchronous CYM74BP54 , synchronous pipelined (CYM74P54, CYM74P55), or synchronous (CYM74SP54, CYM74SP55) configurations with pres­ ence and configuration detect pins

CY2254ASC-2

Abstract: CY27C010 CY82C691 CY82C692 CY82C693 CY82C694 82C691 cy82 processor amd k5
Contextual Info: ADVANCED INFORMATION CY82C690 Pentiumt hyperCachet Chipset DataĆPath/Integrated Cache for hC-ZX Solution Features D D D D Supports all 3.3V PentiumtĆclass processors, AMD K5, and Cyrix M1 CPUs Directly interfaces with CY82C691 and CY82C693 to provide a highĆperformance threeĆchip zero

CY82C691

Abstract: bsram CY2254ASC-2 CY27C010 CY82C692 CY82C694 cy82 "programmable peripheral Interface" pentium amd cpu k5 4Kx64
Contextual Info: hCĆZX/hCĆVX/ ADVANCED INFORMATION hCĆDX Pentium t hyperCachetChipset Family System Features hCĆVX hCĆDX hCĆZX D Value solution with integrated 128ĆKB twoĆway set associative pipelined burst SRAM D Performance solution with 256ĆKB twoĆway set associative pipelined