18.432 B Search Results

z80180 development board

Abstract: Z800 zilog 4114 ram Zilog Z8S180/ESCC Z80182 Z8018200ZCO Z8S180 microtek z80
Contextual Info: SUPPORT PRODUCT Z8018200ZCO DEVELOPMENT KIT DESCRIPTION KIT CONTENTS The Z8018200ZCO kit contains an assembled circuit board, software and documentation to support software and hardware development for the Z80182 system at 18.432 MHz using ASCI0 or MIMIC as COM.Channels

8251 usart

Abstract: USART 8251 8080a 8224 CLOCK intel 8251 USART 8224 intel 8080, 8224, and 8228 intel 8224 intel 8801 baud rate
Contextual Info: inteT 8801 CLOCK GENERATOR CRYSTAL FOR 8224/8080A • Specifically Selected for Intel 8224 ■ Frequency Deviation ±0.005% . 18.432 MHz lor 1.95 8080A Cycle ■ Simple Generation of All Standard Communication Baud Rates . Fundamental Frequency Mode „»

ASM800

Abstract: Z800 zilog Z85230 Z8S180 ASM80 Z8S180 ESCC EVALUATION Zilog Z8S180/ESCC Z8S18000ZCO ASM-80 MCC80
Contextual Info: SUPPORT PRODUCT Z8S18000ZCO STATIC Z180/ESCC EVALUATION BOARD DESCRIPTION KIT CONTENTS The kit contains an assembled circuit board, software and documentation to support software and hardware development for the Z8S180 and Z85230 system at 18.432 MHz. Z8S180/ESCC Evaluation Board

Lm317T1

Abstract: LPT3784 CHW5454 doc2313 AVR atmel 128 kit schematic data sheet 1714 Atmel 122 alphanumeric display 16 pin ALPHANUMERIC DISPLAY image atmel sd card module
Contextual Info: Features • Hardware – ATSTK94 Onboard Features Programmable Switches, LEDs and Alphanumeric Displays Two RS232 Compatible Serial Ports Multiple Clocks 4 MHz, 18.432 MHz, 32.768 kHz and Manual 2-wire Serial Interface for Communication Easy Access to all FPSLIC Pins via Headers

lcd 10 pin

Abstract: 0000-0xDF Siren Sound Generator 5 sound ARM7 instruction set 16C550-style msr 206 magnetic card encoder 0000-n02F HP 4200 CL2803 16C550
Contextual Info: CL-PS7111 Preliminary Data Book FEATURES • Ultra low power Low-Power System-on-a-Chip — Designed for applications that require long battery life while using standard AA/AAA batteries — Average 45 mW/66 mW in normal operation 2.7 V/3.3 V, 13 MHz/18.432 MHz

atmel AT94K manual

Contextual Info: Features • Hardware – ATSTK94 Onboard Features Programmable Switches, LEDs, and Alphanumeric Displays Two RS-232 Compatible Serial Ports Multiple Clocks 4 MHz, 18.432 MHz, 32.768 kHz, and Manual Two-wire Serial Interface for Communication Easy Access to all FPSLIC Pins via Headers

Contextual Info: CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996 D D D D D D D D DB PACKAGE TOP VIEW Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies Two 27-MHz Reference Clock Outputs One 18.432-MHz Reference Clock Output

CDC9171

Contextual Info: CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996 D D D D D D D D DB PACKAGE TOP VIEW Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies Two 27-MHz Reference Clock Outputs One 18.432-MHz Reference Clock Output

PS8106

Contextual Info: fl} PERICOM Precision Clock Generator Description: Features: • • • • • • • • • • Low-cost clock generator Provides precision frequencies for 56K modem applications. Crystal Frequency: 18.432 MHz Provides either 2 clock or 4 clock outputs via mode select

Contextual Info: CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996 D D D D D D D D DB PACKAGE TOP VIEW Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies Two 27-MHz Reference Clock Outputs One 18.432-MHz Reference Clock Output

CDC9171

Contextual Info: CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996 D D D D D D D D DB PACKAGE TOP VIEW Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies Two 27-MHz Reference Clock Outputs One 18.432-MHz Reference Clock Output

LED drivers n51

Abstract: n55F Siren Sound Generator 5 sound ARM7 instruction set n057 B 16C550 CL-PS6700 CL-PS7111 800-0170
Contextual Info: CL-PS7111 'CIRRUS LOGIC • Preliminary D ata Book FEATURES • Ultra low power — Designed for applications that require long battery life while using standard AA/AAA batteries — Average 45 mW/66 mW in normal operation 2.7V/3.3 V, 13 MHz/18.432 MHz — Average 15 mW in idle mode (clock to the CPU stopped,

Contextual Info: CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996 D D D D D D D D DB PACKAGE TOP VIEW Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies Two 27-MHz Reference Clock Outputs One 18.432-MHz Reference Clock Output

1.8432 MHZ CRYSTAL

Abstract: CDC9171
Contextual Info: CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996 D D D D D D D D DB PACKAGE TOP VIEW Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies Two 27-MHz Reference Clock Outputs One 18.432-MHz Reference Clock Output

lcd interfacing with arm7 processor

Abstract: IR LED and photodiode
Contextual Info: CL-PS7111 Product Bulletin FEATURES • Ultra low power — Designed for applications that require long battery life while using standard AA/AAA batteries or rechargeable cells — Average 45 mW/66 mW in normal operation 2.7 V/3.3 V, 13 MHz/18.432 MHz — Average 15 mW in idle mode (clock to the CPU stopped,

1.8432 MHZ CRYSTAL

Abstract: CY26049-36 CY26049ZC-36 CY26049ZC-36T CY26049ZI-36 CY26049ZXC-36 CY26049ZXC-36T
Contextual Info: CY26049-36 FailSafe PacketClock™ Global Communications Clock Generator Features • Fully integrated phase-locked loop PLL • FailSafe output • PLL driven by a crystal oscillator that is phase aligned with external reference • Output frequencies selectable and/or programmed to

CY2410

Abstract: CY26049-36 CY26049ZC-36 CY26049ZC-36T CY26049ZI-36 crystal 18.432mhz 18.432MHZ LOW PROFILE 18.432
Contextual Info: PRELIMINARY CY26049-36 FailSafe PacketClock™ Global Communications Clock Generator Features Benefits • Fully integrated phase-locked loop PLL • Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external

CY26049-36

Abstract: CY26049ZC-36 CY26049ZC-36T CY26049ZI-36 CY26049ZXC-36
Contextual Info: CY26049-36 FailSafe PacketClock™ Global Communications Clock Generator Features • Fully integrated phase-locked loop PLL • FailSafe output • PLL driven by a crystal oscillator that is phase aligned with external reference • Output frequencies selectable and/or programmed to

FS312

Contextual Info: CY26049-36 FailSafe PacketClock Global Communications Clock Generator Features Functional Description • Fully Integrated Phase-Locked Loop PLL ■ FailSafe™ Output ■ 8 kHz Reference Clock ■ PLL Driven by a Crystal Oscillator that is Phase Aligned with

CY24142

Abstract: CY24142-01 CY24142ZC-01 CY24142ZC-01T CY24142ZXC-01 CY24142ZXC-01T
Contextual Info: CY24142 MediaClock Multimedia Clock Generator Features Benefits • Integrated phase-locked loop PLL • Integrated high-performance PLL eliminates the need for • Low-jitter, high-accuracy outputs — external loop filter components • 3.3V operation

CY24142

Abstract: CY24142-01 CY24142ZC-01 CY24142ZC-01T CY24142ZXC-01 CY24142ZXC-01T
Contextual Info: CY24142 MediaClock Multimedia Clock Generator Features Benefits • Integrated phase-locked loop PLL • Integrated high-performance PLL eliminates the need for • Low-jitter, high-accuracy outputs — external loop filter components • 3.3V operation

DMX DECODER IC

Abstract: DMX RECEIVER IC schematic diagram tv sony sony car stereo DMX chip DMX RECEIVER FM STEREO CODER Transponder ID 48 DMX music RECEIVER 4-pin linear hall IC
Contextual Info: ADVANCE INFORMATION DRP 3510A Digital Radio Processor Edition Jan. 16, 1997 6251-410-1AI MICRONAS DRP 3510A ADVANCE INFORMATION Contents Page Section Title 5 6 6 1. 1.1. 1.2. Introduction Main Features Building Blocks 6 2. Functional Description 7 7 7 9 9

CY24141

Abstract: CY24141-3 CY24141ZC-3 q 18.432
Contextual Info: PRELIMINARY CY24141-3 MediaClock Graphics Clock Generator Features Benefits • Integrated phase-locked loop PLL High-performance PLL tailored for multimedia applications • Low-jitter, high-accuracy output Meets critical timing requirements in complex system designs

DMX RECEIVER pcb

Contextual Info: ADVANCE INFORMATION DRP 3510A Digital Radio Processor MICRONAS Edition Jan. 16, 1997 6251-410-1AI DRP 3510A ADVANCE INFORMATION Contents Page Section Title 5 6 6 1. 1.1. 1.2. Introduction Main Features Building Blocks 6 2. Functional Description 7 7 7 9 9