1993 SYNCHRONOUS DRAM JEDEC Search Results

pjuaa

Abstract: 1993 SDRAM 7216B
Contextual Info: 16 777 216 BIT SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY S M 0 S6 82-J A N U A R Y 1993 DGE PACKAG ET TOP VIEW Organization. . . 1M x 8 x 2 Banks 3.3 V-Power Supply (10% Tolerance) Two Banks For On-Chip Interleaving (Gapless Accesses) * High Bandwidth - Up to 100-MHz Data

TMS320AV110

Abstract: AV110 TMS44400 1993 synchronous dram jedec SCSS013C tms320av11
Contextual Info: TMS320AV110 MPEG AUDIO DECODER SCSS013C – MAY 1993 – REVISED AUGUST 1995 • • • • • • • Single-Chip ISO-MPEG Layers 1 and 2 Audio Decoder Decodes Mono, Dual, Stereo, and Joint Stereo Modes Supports All MPEG Sampling and Data Rates, Including Free Format

TMS320AV110

Abstract: tms320av11 tms320av pts 510 AV110 TMS44400 1993 synchronous dram jedec
Contextual Info: TMS320AV110 MPEG AUDIO DECODER SCSS013C – MAY 1993 – REVISED AUGUST 1995 • • • • • • • Single-Chip ISO-MPEG Layers 1 and 2 Audio Decoder Decodes Mono, Dual, Stereo, and Joint Stereo Modes Supports All MPEG Sampling and Data Rates, Including Free Format

266DR

Contextual Info: TMS320AV110 MPEG AUDIO DECODER SCSS013C - MAY 1993 - REVISED AUGUST 1995 • Single-Chip ISO-MPEG Layers 1 and 2 Audio Decoder • 16- or 18-Bit Serial PCM Output Directly Interfaces to Most Serial D/A Converters • Decodes Mono, Dual, Stereo, and Joint

MT48LC2M8S1

Abstract: 1993 synchronous dram jedec A221D 1993 SDRAM
Contextual Info: ADVANCE M T48LC2M 8S1 2 MEG X 8 SDRAM p ilC R O N 3.3 VOLT, PULSED RAS, DUAL BANK, SELF REFRESH FEATURES PIN ASSIGNMENT Top View • Fully synchronous; all signals (excluding clock enable) registered to positive edge of system clock • Dual 1 Meg x 8s, separate, internal banks controlled by A ll

1993 synchronous dram jedec

Abstract: dram ddr 1997 1993 SDRAM
Contextual Info: NEW PRODUCTS 3 128-Mbit DDR SYNCHRONOUS DRAM Yoshitomo Asakura Photo 1 µPD45128842 128Mbit DDR SDRAM NEC has newly developed a world-leading 128-Mb double data rate DDR synchronous DRAM (SDRAM) product (Photo 1) which comes in three configurations. Development Background

266DR

Contextual Info: TMS320AV110 MPEG AUDIO D E C O D E R S C S S 01 3C -M A Y 1 9 9 3 - REVISED AUGUST 1995 * S i ng l e - C h i p I S O - M P E G L a y e r s 1 and 2 A ud i o D e c o d e r * 1 6 - or 1 8-Bit Serial P C M O u t p u t Direct ly I nt e r f a c e s to M o s t Serial D/ A C o n v e r t e r s

A9281

Abstract: 1993 SDRAM ra2t 1993 SDRAM samsung KM48SV2000
Contextual Info: PRELIMINARY CMOS SDRAM KM48SV2000 2M X 8 BIT SYNCHRONOUS DYNAMIC RAM GENERAL DESCRIPTION FEATURES The KM48SV2000 is a 16,777,216 bit synch­ ronous high data rate Dynamic RAM organized as 2,097,152 words by 8bits, fabricated with SAMSUNG'S high performance CMOS technology.

PROCESSOR

Abstract: TMS34082 tms44c251 TMS44C251-10 TMS34020APCM40 TMS34010 TMS34020 74ALS373 equivalent transistor bc 102b SPVU019
Contextual Info: TMS34020, TMS34020A GRAPHICS PROCESSORS SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993 • • • • • • • • • • • Instruction Cycle Time – 100 ns . . . TMS34020A-40 – 125 ns . . . TMS34020-32 – 125 ns . . . TMS34020A-32 Fully Programmable 32-Bit

TMS34082

Abstract: TMS34010 SPVU019 TMS34020 TMS44C251
Contextual Info: TMS34020, TMS34020A GRAPHICS PROCESSORS SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993 • • • • • • • • • • • Instruction Cycle Time – 100 ns . . . TMS34020A-40 – 125 ns . . . TMS34020-32 – 125 ns . . . TMS34020A-32 Fully Programmable 32-Bit

XC3020L

Abstract: XC3030L XC3042L XC3064L XC3090L XC7236A XC7318 KM48SL 1993 synchronous dram jedec XC7336TM
Contextual Info: X-NOTES February 1995 The Programmable Logic Company SM Technical Marketing Series Number 3A Low Voltage Systems LOW VOLTAGE! MIXED VOLTAGE! 3 VOLTS! It's difficult to read the new product press without seeing similar words woven into the headlines. One could be led to believe that the

8207 intel

Abstract: interfacing intel 8086 with ram and rom difference between intel 80186 and intel 80286 pro difference between intel 8086 and intel 80186 pro lt 8207 8207 PEB 2426 ROA20 i8207 iAPX 88 all register
Contextual Info: 8207 DUAL-PORT DYNAMIC RAM CONTROLLER • P rovides All Signais Necessary to Control 16K, 64K and 256K Dynamic RAMs ■ D irectly A ddresses and Drives up to 2 M egabytes w ithout External Drivers ■ Supports Single and Dual-Port Configurations ■ A utom atic RAM Initialization in All

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

Contextual Info: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

Contextual Info: TMS34020, TMS34020A GRAPHICS PROCESSORS SPVS004D - MARCH 1990 - REVISED NOVEMBER 1993 * Instruction Cycle Time - 100 ns . . . TMS34020A-40 - 1 2 5 n s . . .TMS34020-32 - 125 n s . . . TMS34020A-32 145-PIN GB PACKAGE TOP VIEW A B C D E F G H J • Fully Programmable 32-Bit

Contextual Info: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

PEEL programming

Abstract: 22CV10Z-25 22CV10 22CV10A-10 PEEL22CV10 22CV10A PEEL 22CV10A-15 22CV10A-7 22GV10
Contextual Info: PEEL 22GV10 Z A M SEMICONDUCTORS CMOS Programmable Electrically Erasable Logic Device i February 1993 Features General Description Advanced CMOS EEPROM Technology High Performance with Low Power Consumption The AMI PEEL22C V10(Z) is a CMOS Program m able

siplace 80 f4

Abstract: siplace chrysler ic chrysler Siemens Smart Power IC
Contextual Info: Spectrum Semiconductor Group Ambitious goals for the turn of the century Despite deteriorating prices and a weakening market, the Siemens Semiconductor Group can look back on a successful 1995/96 fiscal year, with new orders at DM 4.8 billion, sales of DM 4.7 billion and profits of

TMS34082

Contextual Info: T M S 34020, T M S 3 4 0 2 0 A GRAPHICS PROCESSORS SPVS004D - MARCH 1990 - REVISED NOVEMBER 1993 * * * 1115-PIN GB PACKAGE TOP VIEW Instruction C y cle Tim e - 100 ns . . . T M S 3 4 0 2 0 A - 4 0 - 125 ns . . . T M S 3 4 0 2 0 - 3 2 - 125 ns . . . T M S 3 4 0 2 0 A - 3 2

Mitsubishi transistor C 1588

Abstract: MH64D72KLH-10 MH64D72KLH-75 dram memory module 1993
Contextual Info: Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH64D72KLH-75,-10 4,831,838,208-BIT 67,108,864-WORD BY 72-BIT Double Data Rate Synchronous DRAM Module DESCRIPTION The MH64D72KLH is 67108864 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.

"Lookaside Cache"

Contextual Info: / T T SCS-THOMSON TA125 TECHNICAL ARTICLE Synchronous Burst SRAM for secondary CACHE systems Ricky Tuttle SGS-THOMSON Microelectronics Carrollton, USA The advent of high speed microprocessors and the requirement for high performance systems has opened the door to the Fast SRAM FSRAM mar­

CDC2586

Abstract: MS-026
Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

CDC586

Abstract: MS-026 SCAS336D
Contextual Info: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

HM5221605

Abstract: HM5221605TT-15 HM5221605TT-17 HM5221605TT-20 1993 synchronous dram jedec Hitachi DSA0015
Contextual Info: HM5221605 Series 65,536-word x 16-bit × 2-bank Synchronous Dynamic RAM ADE-203-199B Z Rev. 2.0 Nov. 14, 1996 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5221605 is offered in 2 banks for improved performance.