199Q Search Results

op amp 741 model PSpice

Abstract: op amp 741 model Spice LT1007 LT1078 OP-27 pspice high frequency transistor 741 spice model ERL-M382 OP27
Contextual Info: um Application Note 41 TECHNOLOGY Apr¡| 199Q Questions and Answers on the SPICE Macromodel Library Walt Jung INTRODUCTION This document is provided to answer some of the potential questions raised about the Linear Technology SPICE macromodel library. It assumes that you have a diskette

R301D

Contextual Info: 74ACT11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS145- D3435, MARCH 199Q-REVISEDAPRIL1993 DW OR N PACKAGE * Inputs Are TTL-Voltage Compatible TOP VIEW * Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators * Fully-Buffered Outputs for Maximum

54ACT11004

Abstract: 74ACT11004 D2957 T432
Contextual Info: 31É D TEXAS INSTR LOGIC m 0^^1723 OGÔÔ4SM S « T l i a 54ACT11004, 74ACT11004 HEX INVERTERS " F 4-3 -7-I- 0 0 TI0045— D2957, JANUARY 1988— REVISED MARCH 199Q Flow-Through Architecture to Optimize PCB Layout 1 2 3 4 s gnd C 6 gnd C 7 4YC 8 5YC 9 ó v e 10

D3450

Contextual Info: 74ACT11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS129 - D3450, MARCH 1990 - REVISED APRIL 1993 • * Inputs Are TTL-Voltage Compatible DB, DW OR NT PACKAGE TOP VIEW I * Contains Eight D-Type Flip-Flops I I * Clock Enable Latched to Avoid False Clocking

TQX6273

Abstract: simpson 464 Tele Quartz Group 16.384 MHz Tele Quarz Group Crystal Oscillator HC-49 crystal Tele Quarz Group 16.384 CT 9254 Telcona N1086 30227
Contextual Info: SIEMENS ICs for Communications Framing and Line Interface Component for PCM 30 and PCM 24 FALC54 and FALC-LH PEB 2254 PEB 2255 Crystal recommendation Application Note 12.97 PEB 2255 Revision History : Previous Version : None Page Page Current Version : 12.97

Contextual Info: ML *««93 ADVANCE MICRON I 64K SEMICONDUCTOR. MC SYNCHRONOUS SRAM X MT58LC64K18C4 18 SYNCHRONOUS SRAM 6 4 K x 18 SRAM +3.3V SUPPLY, FULLY REGISTERED INPUTS AND OUTPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • • Fast access times: 7 ,1 0 ,1 2 and 15ns

54ACT11853

Abstract: 74ACT11853 D3474
Contextual Info: 54ACT11853, 74ACT11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D3474, MARCH 1990-REV1SED OCTOBER 1990 54ACT11853 . . . JT PACKAGE 74ACT11853 . . . OW OB NT PACKAGE TOP VIEW High-Speed Bus Transceivers With Parity Generator/Checker Parity-Error-Flag Open-Drain Output

Contextual Info: SN54BCT8374A, SN74BCT8374A SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS SCBSQ45D - JUNE 1990 - REVISED APRIL 1994 I I I • Members of the Texas Instruments SCOPE Family of Testability Products • Octal Test-Integrated Circuits I I • Functionally Equivalent to SN54/74F374

Contextual Info: 74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS _SCAS212- D3447, MARCH 1990-REVISEDAPRIL 1983 Inputs Are TTL-Voltage Compatible OW PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly

MT9LD872G

Contextual Info: 8,16,32 MEG X 72 BUFFERED DRAM DIMMs MICRON I TECHNOLOGY, INC- MT9LD872 X, MT18LD T 1672 X, MT36LD(T)3272 X DRAM MODULE For the latest data sheet revisions, piease referto the Micron Web site: www.micron.com/mti/msp/htmt/ctatasheeLhtml FEATURES PIN ASSIGNMENT (Front View)

SN74ACT8994

Contextual Info: g 1992 SN54ACT8994, SN74ACT8994 DIGITAL BUS MONITORS SCASI96-03604, JULY 1990-REVISED MARCH 1992 Cascaded PSA Mode Allows Compression of Parallel Data Paths Greater Than 16 Bits In Width Direct Memory Access DMA Speeds Memory and Register File Read/Wrtte

zo 103 ma

Abstract: 74ACT11874
Contextual Info: 54ACT11874, 74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS _ D3447. MARCH 1990-REVISED OCTOBER 1990 Inputs are TTL-Voltage Compatible 3-State Buffer-Type Outputs Drive Bus Lines Directly 54ACT11874 . . . JT PACKAGE

D3370

Abstract: SN10KHT5541
Contextual Info: SN10KHT5541 OCTAL ECL-TO-TTL TRANSLATOR WITH 3-STATE OUTPUTS D3370, OCTOBER 1989-REVISED OCTOBER 1990 DW OR NT PACKAGE 10KK Compatible {TOP VIEW ECL and TTL Control Inputs Y1[ Y2[ Y3[ Y4[ Noninverting Outputs Flow-Through Architecture Optimizes PCB Layout

SN100KT5574

Contextual Info: SN100KT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS _ D3418. JANUARY 1990-flEVISED OCTOBER 1990 DW OR NT PACKAGE TO P V IE W * 100K Compatible * ECL Clock and TTL Control Inputs

lexa

Abstract: SN54ACT8997 SN74ACT8997 ct8997
Contextual Info: SN54ACT8997, SN74ACT8997 SCAN PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES _ SCAS157B - APRIL 1990 - REVISED AUGUST 1994 Members of the Texas Instruments SCOPE Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 JTAG Serial Test Bus

Contextual Info: SN54BCT8373A, SN74BCT8373A SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES S C B S 04 4F -JU N E 1990-R E V IS E D JULY 1996 | • [ • • • • • • • Members of the Texas Instruments SCOPE Family of Testability Products Octal Test-Integrated Circuits

SN100KT5539

Abstract: Eel-16 Texas Instruments TTL
Contextual Info: SN100KT5539 OCTAL ECL-TO-TTL TRANSLATOR WITH OPEN-COLLECTOR OUTPUTS _ D 3 4 2 2 , J A N U A R Y 1 9 9 0 - R E V IS E D O C T O B E R 1 9 9 0 DW OR NT PACKAGE 100K Compatible {TOP VIEW Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers

74ACT2158

Abstract: SN74ACT2158 2159s SN74ACT2159 74ACT21 T2159 D32B1
Contextual Info: SN74ACT2158, SN74ACT2159 8K x 9 CACHE ADDRESS COMPARATORS/DATA RAMs D 3281, MAY 19 90-R E V IS E D JUNE 1990 Fast Address to MATCH Delay 22 ns Max TOP V IE W 10 Internal Static RAM On-Chip Address/Data Comparator / * Read Feature with Separate I/O * Word Reset Function for Single Entry

PCF84C00

Abstract: MAB8048 PCF84C21 PCF84C41 PCF84C81 COC11
Contextual Info: T T 3ME D • PCF84C00 PCF84C21/C PCF84C41/C PCF84C81/C 711002b QG11373 3 I PHILIPS INTERNATIONAL 1 BUS " ~ P H P M ct - o a SINGLE-CHIP 8-BIT MICROCONTROLLERS WITH l2C-BUS INTERFACE DESCRIPTION An advanced CMOS process is used to manufacture the PCF84C00, PCF84C21/C, PCF84C41/C and

D3509

Abstract: SN10KHT5573
Contextual Info: SN10KHT5573 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE TRANSPARENT LATCHES AND 3-STATE OUTPUTS _ D3509. MAY t990-REVIS£D OCTOBER 1990 DW OR NT PACKAGE TOP VIEW 10KH Compatible ECL and TTL Control Inputs Noninverting Outputs

SN54BCT8240A

Abstract: SN74BCT8240A
Contextual Info: SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL BUFFERS SCBS067C - FEBRUARY 1990 - REVISED APRIL 1994 Members of the Texas Instruments SCOPE Family of Testability Products Octal Test-Integrated Circuits Functionally Equivalent to SN54/74F240 and SN54/74BCT240 in the Normal­

TA8718N

Abstract: TA8659AN ta8718 ta8659 TA8718N-9 TA8718N-6 ta8659a ta8718k bhc capacitor ind a 1A8718N
Contextual Info: TO SH IBA INTEGRATED CIRCUIT T A 8 7 1 8N TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT TECHNICAL DATA SILICON MONOLITHIC TENTATIVE BATA ^Ir EH-CHROMA-DEFLECT ION SY S T E M FOR A COLOR T E LEVISION PAL). The TA871BN c o m b i n e s a PAT. v i d c o - c h r o m a ^ d c f l e c t i o n

SP 5001 IC INVERTER

Abstract: 555timer schmitt trigger using ic 555 ames 5 op-amp 4136 555timer ic SP 5001 inverter D flip-flop to T Flipflop circuit converter L 296 SP 5001 IC
Contextual Info: ELECTRONIC TECHNOLOGY 2=îE D □ 355G5flb 0QGG141» Q Q E L T C AD20S1 Series CMOS Semicustom Arrays High Output Mixed-mode CMOS 5-Mlcron Sl-gate CMOS Arrays • Analog functions Including Op-amps, voltage references, comparators, oscillators, and analog switches