2 BIT PARITY GENERATOR Search Results

MC10170

Abstract: la 116 diagram
Contextual Info: M O TO R O LA 9 + 2-BIT PARITY G ENERATO R-CH ECKER 9 + 2-BIT PARITY GENERATOR-CHECKER The MC10170 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in

Contextual Info: M MOTOROLA Military 10570 9 + 2-Bit Parity Generator-Checker ELECTRICALLY TESTED PER: MPG 10570 The 10570 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9-bits; that is, Output A goes high

MC-10170

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MCI 0170 The MC10170 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.

OB-90

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MC10170 The MC10170 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.

MC10170

Abstract: MC10160 MC10170FN MC10170L MC10170P
Contextual Info: MC10170 9+2-Bit Parity Generator/ Checker The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate

Contextual Info: 74AC11286 9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS _ D3165, AUGUST 1988 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW * Generates Either Odd or Even Parity for Nine Data Unes * Cascadabie for n-Bits Parity B[ 1 At 2 * Direct Bus Connection for Parity

MC10170

Abstract: T315 MC10170L
Contextual Info: MC10170 9+2-Bit Parity Generator/ Checker The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate

Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32865 FEATURES: DESCRIPTION: • • • • • • • The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed

DL122

Abstract: MC10160 MC10170
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MC10170 The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.

KAG 17 127

Contextual Info: M M O T O R O LA Military 10570 9 + 2-Bit Parity Generator-Checker ELECTRICALLY TESTED PER: MPG 10570 The 10570 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9-bits; that is, Output A go e s high

Contextual Info: SN 54 A S286 , SN 74 A S286 9 BIT PARITY GENERATORS/CHECKER WITH BUS DRIVER PARITY 110 PORT D 2 8 0 9 , DECEM BER 1 9 8 3 - • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Direct Bus Connection for Parity Generation

ICS98ULPA877A

Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

ICS98ULPA877A

Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

160-ball

Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

Contextual Info: HITACHI/ L O G IC/ AR RA YS /M EN ^5 74 HC180 HD D Ë | 4 4 ^ 5 0 3 001 0425 O 92D 1 0 4 2 5 # 8-bit O dd/Even Parity G enerator/C hecker This universal, monolithic, 9-bit 8 data bits plus 1 parity bit parity generator/checker features odd/even outputs and

Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

IDT74SSTU32865

Abstract: SSTU32865
Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

DDR3U

Abstract: SSTE32882 2yn1 DDR3 rdimm pcb layout SSTE32882KA1 DDR3U-1600 da-15 pinout dba1 DDR3 layout DDR3 pcb layout
Contextual Info: DATASHEET Advanced Information 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.

SSTE32882KA1

Contextual Info: DATASHEET Advanced Information 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.

Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

g0517

Contextual Info: NATIONAL SEMICOND {LOGIC* t,l SEMICONDUCTOR 61C 5 1 7 2 4 7- 4 5 - / ? - g g National À jà Semiconductor PRELIM" DM54AS280/DM74ÀS280 9-Bit Parity Generator/Checker General Description These universal, 9-bit parity generators/checkers utilize •

Contextual Info: ADVANCE INFORMATION SN 54F280A, SN 74F2B0A 9 BIT PARITY GENERATORS/CHECKERS 0 2 9 3 2 , M AR C H 1 9 8 7 Generates Either Odd or Even Parity for Nine Data Lines SN 54F2B0A . . J PACKAGE SN 74F280A . . . D OR N PACKAGE TOP VIEW Cascadable for n-Bits Parity

s286

Contextual Info: SN54AS286, SN74AS2B6 9 BIT PARITY GENERATORS/CHECKER WITH BUS DRIVER PARITY I/O PORT D 2 8 0 9 , DECEMBER 1 9 8 3 ~ REVISED AU G U S T 1 9 8 5 • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity S N 54A S286 . . J PACKAGE