20AUG2010 Search Results

Contextual Info: THIS DRAWING IS A CONTROLLED DOCUMENT. LOC REVISIONS DIST - - P LTR A6 B C C1 C2 1 3 DESCRIPTION Tolerance added Change marking Printing Printing Date-Code drawing logo change 4 5 DWN DATE HD HD HD HD PH UKo UKo UKo UKo ZC 09SEP2009 11SEP2009 10MAY2010 20AUG2010

CD4011UB

Abstract: CD4011UBE CD4011UBEE4 CD4011UBF CD4011UBM CD4011UBM96 CD4011UBM96E4 CD4011UBM96G4 CD4011UBME4 CD4011UBMG4
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS022D – Revised September 2003 The CD4011UB types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes),

A115-A

Abstract: C101 SN54LV393A SN74LV393A
Contextual Info: SN54LV393A, SN74LV393A DUAL 4ĆBIT BINARY COUNTERS SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

CD4069UBE

Abstract: CD4069UBEE4 CD4069UBF CD4069UBF3A CD4069UBM CD4069UBM96 CD4069UBM96E4 CD4069UBM96G4 CD4069UBME4 CD4069UBMG4
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS054C – Revised September 2003 The CD4069UB-Series types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline

Contextual Info: SN54HC27, SN74HC27 TRIPLE 3-INPUT POSITIVE-NOR GATES SCLS088D – DECEMBER 1982 – REVISED AUGUST 2003 D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC Typical tpd = 9 ns ±4-mA Output Drive at 5 V

A115-A

Abstract: C101 PCA9556 PCA9557 PCA9557RGVR
Contextual Info: PCA9557 www.ti.com. SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER

A115-A

Abstract: C101 LV123A SN54LV123A SN74LV123A SCLS393O
Contextual Info: SN54LV123A, SN74LV123A DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext 1 16

A115-A

Abstract: C101 SN54LV4066A SN74LV4066A SN74LV4066AN V2175
Contextual Info: SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 1A 1B 2B 2A 2C 3C GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 4C 4A 4B 3B 3A SN74LV4066A . . . RGY PACKAGE TOP VIEW description/ordering information

CD4007UB

Abstract: CD4007UBE CD4007UBEE4 CD4007UBF CD4007UBF3A CD4007UBF3A116 CD4007UBM CD4007UBM96 CD4007UBM96E4 CD4007UBM96G4
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS018C – Revised September 2003 The CD4007UB types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes),

CD54HCT03

Abstract: CD54HCT03F3A CD74HC03 CD74HCT03 CT03 CD54HC03 CD54HC03F3A
Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126D High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised September 2003

CD54HC280

Abstract: CD54HCT280 CD74HC280 CD74HCT280 HC280 LS180
Contextual Info: [ /Title CD74 HC280 , CD74 HCT28 0 /Subject (High Speed CMOS Logic 9-Bit Odd/E ven Parity CD54HC280, CD74HC280, CD54HCT280, CD74HCT280 Data sheet acquired from Harris Semiconductor SCHS175D High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker November 1997 - Revised October 2003

CD4081B-MIL

Abstract: 17001bca CD4073B-MIL
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS057C – Revised September 2003 The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead

Contextual Info: SPEAr1310 Dual-core Cortex A9 embedded MPU for communications Data brief Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – Supporting both symmetric SMP and asymmetric (AMP) multiprocessing – 32+32 KB L1 Instructions/Data cache per

CD4020B

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS030D − Revised December 2003 The CD4020B and CD4040B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffix , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline

AN 17823

Abstract: AN 17823 A 17823 A ERNI 284697 17823 SWIM stm32 STM8 SWIM ERNI STLink 20 pin JTAG CONNECTOR
Contextual Info: ST-LINK In-circuit debugger/programmer for STM8 and STM32 Data brief Features • 5 V power supplied by USB connector ■ USB 2.0 full speed interface compatible ■ USB standard A to Mini-B cable provided ■ SWIM specific features: – 1.65 V to 5.5 V application voltage

CD4068BE

Abstract: CD4068BM96 CD4068BM96E4 CD4068BM96G4 CD4068BME4 CD4068B CD4068BEE4 CD4068BF CD4068BF3A CD4068BM
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS053C – Revised September 2003 The CD4068B types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT,

Contextual Info: SN54HC20, SN74HC20 DUAL 4ĆINPUT POSITIVEĆNAND GATES SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC20 . . . FK PACKAGE

Contextual Info: SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003 D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC Typical tpd = 10 ns D

DAP 011 regulator

Abstract: b0264 TAS570x GDE TAS5715
Contextual Info: TAS5715 www.ti.com SLOS645 – AUGUST 2010 25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC Check for Samples: TAS5715 FEATURES 1 • • • Audio Input/Output – 25-W Into an 8-Ω Load From an 18-V Supply – 50-W Support in PBTL Mode With 4-Ω Load

Contextual Info: SN54LV4052A, SN74LV4052A DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS429H − MAY 1999 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Support Mixed-Mode Voltage Operation on 2Y0 2Y2 2-COM 2Y3 2Y1 INH GND GND 1 16 2 15 3 14 4 13 5 12 6 11 7

Contextual Info: SN54LVC06A, SN74LVC06A HEX INVERTER BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS www.ti.com SCAS596N – OCTOBER 1997 – REVISED JULY 2005 FEATURES • • Operate From 1.65 V to 3.6 V Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS030D − Revised December 2003 The CD4020B and CD4040B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffix , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline

Contextual Info: SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003 D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC Typical tpd = 10 ns D

Contextual Info: SN54LV273A, SN74LV273A OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCLS399J − APRIL 1998 − REVISED APRIL 2005 D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV Output VOH Undershoot >2.3 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation