20D20J Search Results

PAL16L8 programming algorithm

Abstract: Intel N85C224 EP330 P85C220 n85c220 PAL20L8 programming specifications 16v8 programming IC PALCE16 palc20r 20V8
Contextual Info: in tj, 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED TSU, TSo 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features: • Low-Power, High-Performance Upgrade for SSI/MSI Logic and Bipolar PALs* High-Performance Systems

PAL16L8 programming algorithm

Abstract: N85C220 85C220 pal16r8 programming algorithm 85C224-66 D85C220-66 intel PLD d85c220 gal 16v8 programming algorithm
Contextual Info: in te i 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED TSU, TS0 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features: • Low-Power, High-Performance Upgrade for SSI/MSI Logic and Bipolar PALs* High-Performance Systems

Contextual Info: 85C220/85C224-7 AND -10 FAST TpD, HALF-POWER 8-MACROCELL PLDs These Combinatorial Optimized Timing PLDs Offer Superior Design Features: • High-Performance Low-Power Upgrade for -7 and -10 Bipolar/CMOS* PLD’s in High-Performance Systems ■ tpo 7.5 ns, 74 MHz Frequency with

Contextual Info: M85C220 FAST 1-MICRON CHMOS 8-MACROCELL jmPLD Military m High-Performance, Low-Power Upgrade • ■ ■ ■ ■ See Packaging Spec., Order #231368 ■ Military Temperature Range: —55°C to +125°C(Tc) O Csi cs o in 00 2 IN P 1 /C L K C 1 IN P 2 C 2 IN P 3 C

Q07S

Abstract: 18CV EZ-319 p85c22066 ep330 85C220 intel PLD 290134 p85c220-80
Contextual Info: INTEL CORP intgJ Mû Sb 17b 00721=52 7 MME D MEMORY/PLD/ XTL2 85C220-80 FAST 1-MICRON CHMOS 8-MACROCELL jmPLD High-Performance, Low-Power Upgrade for SSI/MSI Logic and Bipolar PALs* in lntel386TM, 1486TM, i860 , 80960 Series, and Other High-Performance Systems

PAL16L8 programming algorithm

Abstract: 85c220 P85C220-10 n85c224-7 74s* programming AMD palce16v8 programming intel PLD 290134 intel Series Gate Array palce16v8 programming algorithm
Contextual Info: 85C220/85C224-7 AND -10 FAST T pd, HALF-POWER 8-MACROCELL PLDs These Combinatorial Optimized Timing PLDs Offer Superior Design Features: • High-Performance Low-Power Upgrade for -7 and -10 Bipolar/CMOS* PLD’s in High-Performance Systems ■ tpo 7.5 ns, 74 MHz Frequency with

Contextual Info: in te i M85C220 FAST 1-MICRON CHMOS 8-MACROCELL juPLD Military High-Performance, Low-Power Upgrade for SSI/MSI Logic and Bipolar PALs* in intei386TM, ¡4 8 6 tm , ¡860tm , 80960 Series, and Other High-Performance Systems Typical Ice = 35 mA at 15 MHz Emulates 20-pin PAL Architectures

PAL16L8 programming algorithm

Abstract: 85C220 P85C220-7
Contextual Info: IP tS O G Ä M f in te i 85C220/85C224-7 AND -10 COMBINATORIAL OPTIMIZED TIMING FAST 1-MICRON CHMOS 8-MACROCELL jaPLDs These Combinatorial Optimized Timing jaPLDs Offer Superior Design Features: 8 P-Terms, Selectable SOP Invert, OE P-Term for Each Macrocell

1NP2

Abstract: iUP-200 PALC20L8 PAL16L8 programming algorithm N85C224-80 290134 29013 P85C220-80 PAL20L8 programming specifications N85C224
Contextual Info: in tj, 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED TSU, TSo 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features: • Low-Power, High-Performance Upgrade for SSI/MSI Logic and Bipolar PALs* High-Performance Systems