20MHZT Search Results

oled note

Abstract: TLA100-3E aui isolation transformer L0323 L0323-A
Contextual Info: Advance Data Sheet M icroelectronics T7220A Twisted-Pair Medium Attachment Unit TPMAU2 Issue 0.2 Features Description • Compliance with IEEE 802.3 standards* for AUIinterface The T7220A Twisted-Pair Medium Attachment Unit (TPMAU2) simplifies the design and implementation

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3954; Rev 1; 10/06 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

ANSI/TIA/EIA-644

Abstract: MAX9232 MAX9232EUM
Contextual Info: XX-XXXX; Rev 0; 9/05 Programmable Spread-Spectrum and DC-Balance 21-Bit Deserializer Features The MAX9232 deserializes three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock provides the timing for deserialization. The MAX9232 features spread-spectrum capability, allowing the output data and clock

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

150pf 6kv

Abstract: MAX9242 MAX9242EUM MAX9246
Contextual Info: 19-3954; Rev 3; 2/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

150pf 6kv

Abstract: MAX9242 MAX9242EUM MAX9246
Contextual Info: 19-3954; Rev 4; 7/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

C164

Abstract: C164CI DIP-40 PCA82C251 Funkamateur amd 29F010 flash memory amd 29f040 MCTC02
Contextual Info: DIPmodul-164 Hardware-Manual Ausgabe September 2000 Ein Produkt eines Unternehmens der PHYTEC Technologie Holding AG DIPmodul-164 Im Buch verwendete Bezeichnungen für Erzeugnisse, die zugleich ein eingetragenes Warenzeichen darstellen, wurden nicht besonders gekennzeichnet. Das

150pf 6kv

Abstract: MAX9242 MAX9242EUM MAX9246
Contextual Info: 19-3954; Rev 4; 7/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock

MAX9242EUM

Abstract: MAX9242 MAX9246
Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

C164CI

Abstract: PCA82C251 C164 DIP40 Funkamateur
Contextual Info: DIPmodul 164 Hardware Manual Ausgabe Januar 2002 Ein Produkt eines Unternehmens der PHYTEC Technologie Holding AG DIPmodul 164 Im Buch verwendete Bezeichnungen für Erzeugnisse, die zugleich ein eingetragenes Warenzeichen darstellen, wurden nicht besonders gekennzeichnet. Das

MAX9217

Abstract: MAX9247 MAX9248 MAX9250 MAX9250ECM MAX9250ETM 3248L
Contextual Info: 19-3943; Rev 0; 1/06 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

direct sequence spread spectrum

Abstract: 150pf 6kv MAX9209 MAX9213 MAX9242 MAX9246
Contextual Info: 19-3954; Rev 0; 1/06 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance The MAX9242/MAX9244/MAX9246 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock provides the timing for deserialization. The MAX9242/

Contextual Info: 19-3954; Rev 4; 7/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock