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    210PS Search Results

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    210PS Price and Stock

    PEI Genesis PT01A12-10P-SR

    PT 10C 10#20 PIN RECP
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    DigiKey PT01A12-10P-SR Bag 291 1
    • 1 $31.08
    • 10 $26.94
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    PEI Genesis PT00E12-10P-SR

    PT 10C 10#20 PIN RECP
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    DigiKey PT00E12-10P-SR Bag 252 1
    • 1 $28.59
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    PT00E12-10P-SR Bag 33 1
    • 1 $31.82
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    PEI Genesis PT06SE12-10P-SR

    PTSE 10C 10#20 PIN PLUG
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    DigiKey PT06SE12-10P-SR Bag 194 1
    • 1 $46.5
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    PEI Genesis PT06SE12-10P-SR-LC

    CONN PLUG HSG MALE 10POS INLINE
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    DigiKey PT06SE12-10P-SR-LC Bulk 194 1
    • 1 $38.9
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    Amphenol Industrial Operations PT06E-12-10P(SR)

    CONN PLUG MALE 10P GOLD SLDR CUP
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    DigiKey PT06E-12-10P(SR) Bulk 181 1
    • 1 $37.21
    • 10 $28.759
    • 100 $22.6226
    • 1000 $19.6
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    Newark PT06E-12-10P(SR) Bulk 10 1
    • 1 $35.78
    • 10 $31.55
    • 100 $27.34
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    RS PT06E-12-10P(SR) Bulk 131 1
    • 1 $34.19
    • 10 $28.55
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    Master Electronics PT06E-12-10P(SR)
    • 1 -
    • 10 $25.46
    • 100 $20.96
    • 1000 $19.74
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    210PS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: SEPTEMBER 1993 DS3820 - 2.0 CLA80000 SERIES HIGH DENSITY CMOS GATE ARRAYS INTRODUCTION ARRAY SIZES The new CLA80k gate array series from GEC Plessey Semiconductors offers advantages in speed and density over previous array series. The unique architecture allows


    Original     		PDF DS3820 CLA80000 CLA80k

    Untitled

    Abstract: No abstract text available
    Text: SY89847U 1.5GHz Precision, LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination General Description The SY89847U is a 2.5V, 1:5 LVDS fanout buffer with a 2:1 differential input multiplexer MUX . A unique Fail-Safe Input (FSI) protection prevents


    Original     		PDF SY89847U SY89847U 100mV) 100mV 200mVPP) M9999-060107-B

    CDKD0105

    Abstract: CDKD0505 CDKD1505 CDKD5005 CDKD3505 CDKD4505 CDKD2005 CDKD1005 CDKD1205 CDKD0605
    Text: Differential Delay Lines CDKD LTCC Multi-layered Differential Delay Lines C D K D - t y p e d e l a y l i n e i s a n LT C C L o w Te m p e r a t u r e C o - f i r e d C e r a m i c c h i p - t y p e d i ff e r e n t i a l d e l a y l i n e . I t c o v e r s 1 / 4 o f t h e a r e a


    Original     		PDF 200MHz 094002B/09 CDKD0105 CDKD0505 CDKD1505 CDKD5005 CDKD3505 CDKD4505 CDKD2005 CDKD1005 CDKD1205 CDKD0605

    AD8352ACPZ-WP

    Abstract: amplifier 10 ghz AD8352 AD9445 CP-16-3 ETC1-1-13 MO-220-VEED-2
    Text: 2 GHz Ultralow Distortion Differential RF/IF Amplifier AD8352 FEATURES FUNCTIONAL BLOCK DIAGRAM VCM VCC BIAS CELL ENB RGP RDP RG VIP CD + VOP – VON RD VIN RDN 05728-001 GND RGN AD8352 44 –65 42 APPLICATIONS –70 40 Differential ADC drivers Single-ended-to-differential conversion


    Original     		PDF AD8352 AD8352ACPZ-R71 AD8352ACPZ-R21 AD8352-EVALZ1 16-Lead CP-16-3 AD8352ACPZ-WP amplifier 10 ghz AD8352 AD9445 CP-16-3 ETC1-1-13 MO-220-VEED-2

    T-CON Schematic

    Abstract: IC ADC 0804 -4-bit pin details t-con lvds schematic diagram TCON lcd sharp DELTA 18AF SCHEMATIC scaler mcu lvds diagram Sharp TCON ADE3800 TFT LCD timing controller T-con DUAL PIXEL ade3800xl ic
    Text: ADE3800 Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters • Low power 0.15 µm process technology ■ Low cost 100-pin LQFP and 128-pin LQFP packages ■ Lead-free versions available in 2005. Feature Overview


    Original     		PDF ADE3800 10-bit 100-pin 128-pin ADE3800 ADE3800XL T-CON Schematic IC ADC 0804 -4-bit pin details t-con lvds schematic diagram TCON lcd sharp DELTA 18AF SCHEMATIC scaler mcu lvds diagram Sharp TCON TFT LCD timing controller T-con DUAL PIXEL ade3800xl ic

    ICS86962CYI-01

    Abstract: ICS86962CYI01 ICS86962CYI-01T ICS86962I-01 MS-026 60-110-MHz
    Text: ICS86962I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVCMOS/LVTTL ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS86962I-01 is a low voltage, low skew LVCMOS/LVTTL Zero Delay Buffer and a memHiPerClockS ber of the HiPerClockS™ family of High Performance Clock Solutions from ICS. With output


    Original     		PDF ICS86962I-01 1-TO-18 ICS86962I-01 140MHz, 86962CYI-01 ICS86962CYI-01 ICS86962CYI01 ICS86962CYI-01T MS-026 60-110-MHz

    prbs pattern generator using vhdl

    Abstract: BUT16
    Text: LatticeECP2/M Family Handbook HB1003 Version 04.9, April 2011 LatticeECP2/M Family Handbook Table of Contents April 2011 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1


    Original     		PDF HB1003 TN1113 TN1149 TN1102 TN1103 TN1105 TN1107 TN1108 TN1109 TN1124 prbs pattern generator using vhdl BUT16

    8 bit alu in vhdl mini project report

    Abstract: DDR3 layout guidelines lfe3-17ea-6fn484c lfe3-35 LFE3-17EA-7FTN256C LFE3-17EA-6FTN256C HB1009 LFE3-70EA-6FN672C DDR3 layout LFE395
    Text: LatticeECP3 Family Handbook HB1009 Version 04.1, January 2012 LatticeECP3 Family Handbook Table of Contents January 2012 Section I. LatticeECP3 Family Data Sheet Introduction Features . 1-1


    Original     		PDF HB1009 TN1176 TN1179 TN1189 TN1180 TN1178 8 bit alu in vhdl mini project report DDR3 layout guidelines lfe3-17ea-6fn484c lfe3-35 LFE3-17EA-7FTN256C LFE3-17EA-6FTN256C LFE3-70EA-6FN672C DDR3 layout LFE395

    Untitled

    Abstract: No abstract text available
    Text: LatticeECP2/M Family Handbook HB1003 Version 02.2, February 2007 LatticeECP2/M Family Handbook Table of Contents February 2007 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1


    Original     		PDF HB1003 TN1106 TN1103 TN1149.

    Untitled

    Abstract: No abstract text available
    Text: SY89847U 1.5GHz Precision, LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination General Description The SY89847U is a 2.5V, 1:5 LVDS fanout buffer with a 2:1 differential input multiplexer MUX . A unique Fail-Safe Input (FSI) protection prevents


    Original     		PDF SY89847U SY89847U 100mV) 100mV 200mVPP) M9999-060107-B

    MT41K64M16

    Abstract: No abstract text available
    Text: 1Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM MT41K256M4 – 128 Meg x 4 x 8 banks MT41K128M8 – 64 Meg x 8 x 8 banks MT41K64M16 – 32 Meg x 16 x 8 banks • TC of 0°C to 95°C – 64ms, 8192-cycle refresh at 0°C to 85°C – 32ms at 85°C to 95°C


    Original     		PDF MT41K256M4 MT41K128M8 MT41K64M16 8192-cycle 09005aef833b7221 MT41K64M16

    Untitled

    Abstract: No abstract text available
    Text: 2Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM MT41K512M4 – 64 Meg x 4 x 8 banks MT41K256M8 – 32 Meg x 8 x 8 banks MT41K16M16 – 16 Meg x 16 x 8 banks • • • • Description The 1.35V DDR3L SDRAM device is a low-voltage version of the 1.5V DDR3 SDRAM device. Refer to the


    Original     		PDF MT41K512M4 MT41K256M8 MT41K16M16 78-ball 78-ball 96-ball 09005aef83ed2952

    L-SG1010-A3

    Abstract: SG1010-A3 tx5n 100OHM REF10 SG1010 SG2010 StarGen pci
    Text: SG1010 Data Sheet Revision Information: 5.1 StarGen, Inc., 225 Cedar Hill Street, Suite 22, Marlborough, MA 01752 www.stargen.com October 2004 StarGen, Inc. believes the information in this publication is correct; however, the information is subject to change


    Original     		PDF SG1010 SG1010-A3 L-SG1010-A3 L-SG1010-A3 SG1010-A3 tx5n 100OHM REF10 SG2010 StarGen pci

    Untitled

    Abstract: No abstract text available
    Text: SY89847U 1.5GHz Precision, LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination General Description The SY89847U is a 2.5V, 1:5 LVDS fanout buffer with a 2:1 differential input multiplexer MUX . A unique Fail-Safe Input (FSI) protection prevents


    Original     		PDF SY89847U SY89847U 100mV) 100mV 200mVPP) M9999-060107-B

    Power Supply PS-613 uk

    Abstract: CQFP44 GP141 DS3820 mux2*1 hp 4552 PSOP28-MP0818 cla85xxx PS-3306 Series Mitel Semiconductor process flow
    Text: CLA80000 SERIES HIGH DENSITY CMOS GATE ARRAYS DS3820-2.1 July 1997 INTRODUCTION ARRAY SIZES The CLA80k gate array series from Mitel Semiconductor offers advantages in speed and density over previous array series. Improvements in design combined with advances in


    Original     		PDF CLA80000 DS3820-2 CLA80k 210ps Power Supply PS-613 uk CQFP44 GP141 DS3820 mux2*1 hp 4552 PSOP28-MP0818 cla85xxx PS-3306 Series Mitel Semiconductor process flow

    MT41K64M16

    Abstract: No abstract text available
    Text: Preliminary‡ 1Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM MT41K256M4 – 128 Meg x 4 x 8 banks MT41K128M8 – 64 Meg x 8 x 8 banks MT41K64M16 – 32 Meg x 16 x 8 banks • Write leveling • Multipurpose register • Output driver calibration Description


    Original     		PDF MT41K256M4 MT41K128M8 MT41K64M16 78-ball 09005aef833b7221 MT41K64M16

    Untitled

    Abstract: No abstract text available
    Text: SY89847U 1.5GHz Precision, LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination PRELIMINARY Rev. 12/18/06-A General Description The SY89847U is a 2.5V, 1:5 LVDS fanout buffer with a 2:1 differential input multiplexer MUX . A unique Fail-Safe Input (FSI) protection prevents


    Original     		PDF SY89847U 12/18/06-A SY89847U 100mV) 100mV 200mVPP) M9999-121806-A

    CG51364

    Abstract: CG51284 CG51114 CG51754 CG51214 CG51484 CG51654 fujitsu asic quad design motive
    Text: November 1995 Edition 1.5 DATA SHEET CG51/CE51 SERIES 3V, 0.50 MICRON HIGH PERFORMANCE/LOW POWER CMOS GATE ARRAYS DESCRIPTION The Fujitsu CG51/CE51 is a series of ultra high performance CMOS gate arrays. The CG51 is a high density Sea-of-Gates array for applications requiring high levels of integration or low


    Original     		PDF CG51/CE51 Th5431 ASIC-DS-20084-11/95 CG51364 CG51284 CG51114 CG51754 CG51214 CG51484 CG51654 fujitsu asic quad design motive

    AQS210PS

    Abstract: AQV214E Application transistor aqy sensor matsushita aqv214 AQS210T2S AQS210TS AQV251 AQS821HS AQV210S AQW210S
    Text: PhotoMOSRelay Products for use in Modems is the worldwide brand name of automation control products from Matsushita Electric Works. Long life, high –reliability PhotoMOS relays– Playing an important role in fundamental telecommunication PhotoMOS relays combine the advantages of solid-state relays with those of mechanical relays. Our wide array of


    Original     		PDF I-37012 CH-6343 ACG-C0274-E-1 AQS210PS AQV214E Application transistor aqy sensor matsushita aqv214 AQS210T2S AQS210TS AQV251 AQS821HS AQV210S AQW210S

    TDS794D

    Abstract: OCX1601 OCX160 Crosspoint Switches I-CUBE
    Text: Technical Note Measuring Duty Cycle Distortion in the OCX160 1.0 Introduction The differential clock and I/O nature of the OCX160 make this device ideal in data communication applications for transmitting data, video, or audio information. This application note discusses noise effects


    Original     		PDF OCX160 OCX160 OCX160, TDS794D OCX160-- OCX1601 Crosspoint Switches I-CUBE

    Untitled

    Abstract: No abstract text available
    Text: LatticeECP3 Family Handbook HB1009 Version 04.9, August 2012 LatticeECP3 Family Handbook Table of Contents August 2012 Section I. LatticeECP3 Family Data Sheet Introduction Features . 1-1


    Original     		PDF HB1009 TN1177 TN1176 TN1178 TN1180 TN1169

    lattice ECP3 Pinouts files

    Abstract: No abstract text available
    Text: LatticeECP3 Family Handbook HB1009 Version 04.7, June 2012 LatticeECP3 Family Handbook Table of Contents June 2012 Section I. LatticeECP3 Family Data Sheet Introduction Features . 1-1


    Original     		PDF HB1009 TN1189 TN1177 TN1176 TN1178 lattice ECP3 Pinouts files

    Untitled

    Abstract: No abstract text available
    Text: SY89835U 2.5V, 2GHz 3.2 Gbps Ultra-Precision, Differential 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input General Description The SY89835U is a 2.5V, high-speed 2GHz differential Low Voltage Differential Swing (LVDS) 1:2 fanout buffer


    Original     		PDF SY89835U SY89835U M9999-020706

    Untitled

    Abstract: No abstract text available
    Text: Data Sheet January 1998 m icroelectronics group Lucent Technologies Bell Labs Innovations T7256 Single-Chip NT1 SCNT1 Transceiver Features • U- to S/T-interface conversion for ISDN basic rate (2B+D) systems — Integrated U- and S/T-interfaces — Operates in stand-alone mode to provide U- and


    OCR Scan     		PDF T7256 F-06561