22SEP2009 Search Results

STM32F103xE

Abstract: LQPF100 FOOTPRINTS BGA64 LQFP100 LQFP48 LQFP64 STM32F103C8 STM32F103RB AN2606 STM32F103CBT6
Contextual Info: STM32F103x8 STM32F103xB Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1

STM32 LQFP-64 footprint

Abstract: rain alarm CIRCUIT using IC 555 vfQFPn-36 footprint LQFP100 LQFP48 LQFP64 STM32F101 QFN-36 STM32F10xxx jtag
Contextual Info: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1 performance at 0 wait state memory

B.A 2ND HP DATE SHEET 2011

Abstract: DAC5682Z DAC5681Z DAC5681ZIRGCR DAC5681ZIRGCT
Contextual Info: DAC5681Z www.ti.com. SLLS865B – AUGUST 2007 – REVISED MARCH 2009 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER DAC

DVD optical pick-up assembly

Abstract: LQM21PN2R2 Laser Diode for dvd 500 mW PCB GSM ANTENNA G003 TPA6141A2 TPA6141A2YFFR TPA6141A2YFFT DVD laser pickup assembly
Contextual Info: TPA6141A2 www.ti.com. SLOS634A – MARCH 2009 – REVISED AUGUST 2009 CLASS-G DIRECTPATH STEREO HEADPHONE AMPLIFIER

DAC5688

Abstract: DAC5689 DAC5689IRGCR DAC5689IRGCT
Contextual Info: DAC5689 www.ti.com . SLLS989 – SEPTEMBER 2009 16-BIT, 800 MSPS 2x–8x INTERPOLATING DUAL-CHANNEL

Contextual Info: TPS22921, TPS22922, TPS22922B www.ti.com. SLVS749A – NOVEMBER 2008 – REVISED DECEMBER 2008 LOW INPUT VOLTAGE, ULTRA-LOW rON LOAD SWITCHES

Contextual Info: TPS62400, TPS62401 TPS62402, TPS62403, TPS62404 www.ti.com SLVS681E – JUNE 2006 – REVISED APRIL 2010 2.25MHz 400mA/600mA Dual Step-Down Converter In Small 3x3mm QFN Package Check for Samples: TPS62400, TPS62401, TPS62402, TPS62403, TPS62404 FEATURES 1

UCC2895 application

Abstract: uc3875 application note UC3879 application notes ucc3895 application note SLUA246
Contextual Info: UCC1895 UCC2895 UCC3895 SLUS157O - DECEMBER 1999 - REVISED APRIL 2010 BiCMOS ADVANCED PHASE-SHIFT PWM CONTROLLER FEATURES D Programmable Output Turn-on Delay D Adaptive Delay Set D Bidirectional Oscillator Synchronization D Voltage-Mode, Peak Current-Mode, or

74LVC1G126DBVRE4

Abstract: A115-A C101 SN74LVC1G126
Contextual Info: SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES224N – APRIL 1999 – REVISED FEBRUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

PWM by using dsp F2812

Abstract: hp 7540 monitor circuit diagram F2812 SM320F2812 TMS320C2000 TMS320x281x Event Manager EV Reference Guide TMS320x281x DSP Event Manager EV Reference IFR 9540 M421 30 327 9540
Contextual Info: SM320F2812-HT Digital Signal Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Contextual Info: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1 performance at 0 wait state memory

PH6N

Abstract: TRANSISTOR PH6N transistor ph4n
Contextual Info: SPEAr600 Embedded MPU with dual ARM926 core, flexible memory support, powerful connectivity features and programmable LCD interface Datasheet − production data Features • Dual ARM926EJ-S core up to 333 MHz: – Each with 16 Kbytes instruction cache + 16

SN74LVC1G

Abstract: SN74LVC1G79-EP A115-A C101 SN74LVC1G79 SN74LVC1G79YZPR
Contextual Info: SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S – APRIL 1999 – REVISED NOVEMBER 2007 FEATURES 1 • Available in the Texas Instruments NanoFree Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V

Contextual Info: 4 THIS DRAWING 3 IS U N P U B LIS H E D . COPYRIGHT RELEASED BY TE ELECTRONICS CORPORATION. FOR PUBLICATION A LL RIGHTS 2 - ,- LOC R ESERVED. R E V IS IO N S D IST D p LTR D E SC RIPTIO N D REVISED. ECR—0 9 —0 2 0 9 5 1 DATE DWN APVD 22SEP09 FY WK

FX-702-SYNCE-156M250000

Abstract: FX-702 IR detector LFN IR LFN IR LFN detector LFN ir
Contextual Info: FX-702-SYNCE-156M250000 Complete VCSO Based Phase Lock Loop For Synchronous Ethernet Jitter Attenuation FX-702 Description The FX-702 is a low jitter precision frequency translator that provides clock smoothing/jitter attenuation of a 156.25 MHz input clock. The FX-702’s superior jitter performance is achieved through the PLL’s integrated VCSO. The FX-702 is housed in a

STM32F102x8

Abstract: STM32F1 stm32f102 manual stm32f102 stm32f102 reference manual stm32f102c AN2606 stm32 STM32F102xB AN2606 LQFP48
Contextual Info: STM32F102x8 STM32F102xB Medium-density USB access line, ARM-based 32-bit MCU with 64/128KB Flash, USB FS interface, 6 timers, ADC & 8 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1

Contextual Info: STM32F102x8 STM32F102xB Medium-density USB access line, ARM-based 32b MCU with 64/128KB Flash, USB FS, 6 timers, ADC & 8 com. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1

Contextual Info: ADS8556 ADS8557 ADS8558 www.ti.com . SBAS404A – OCTOBER 2006 – REVISED AUGUST 2009 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling

Contextual Info: TPA6141A2 www.ti.com. SLOS634A – MARCH 2009 – REVISED AUGUST 2009 CLASS-G DIRECTPATH STEREO HEADPHONE AMPLIFIER

transistor PH6n

Abstract: transistor PH7n ph5n PH6N transistor ph4n transistor ph0n ph7n ph1n lk1 K20 transistor ph5n
Contextual Info: SPEAr600 Embedded MPU with dual ARM926 core, flexible memory support, powerful connectivity features and programmable LCD interface Features • Dual ARM926EJ-S core up to 333 MHz: – Each with 16 Kbytes instruction cache + 16 Kbytes data cache ■ High performance 8-channel DMA

Contextual Info: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1

Contextual Info: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Datasheet − production data Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1

Contextual Info: VN920-E Single-channel high side driver Features Type RDS on IOUT VCC VN920-E VN920-12-E 16 mΩ 30 A 36 V PENTAWATT • CMOS compatible input ■ Proportional load current sense ■ Shorted load protection ■ Under voltage and overvoltage shutdown ■ Overvoltage clamp

hp 8133A

Abstract: B.A 2ND HP DATE SHEET 2011 NO1X4 DAC5681Z DAC5682Z rf power detector dynamic range CDMA DAC5681ZIRGCR DAC5681ZIRGCT
Contextual Info: DAC5681Z www.ti.com . SLLS865C – AUGUST 2007 – REVISED JUNE 2009 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING