2305 IDT Search Results

BU2305

Abstract: BU2305F bu2302
Contextual Info: Standard iCs CR timer BU2302/BU2302F/BU2305/BU2305F The B U 2302/F and B U 2305/F are general-purpose ICs used in timers. The tim er off tim e is based on the oscillation frequency that is determ ined by the external CR connected to the internal oscillator circuit.

AN-229

Abstract: IDT2305 IDT2308 IDT2308-1 IDT2308-1H IDT2308-2 IDT2308-3 IDT2308-4 IDT2309 2308
Contextual Info: APPLICATION NOTE AN-229 ZERO DELAY BUFFERS APPLICATION NOTE AN-229 ZERO DELAY BUFFERS WHAT IS A ZERO DELAY BUFFER? WHAT IS THE IDT2305, IDT2308 AND IDT2309? A zero delay buffer is a device that can fan out one clock signal into multiple clock signals, with zero delay and very low skew between the

transistor cross ref

Abstract: AN-229 IDT2305 IDT2308 IDT2308-1 IDT2308-1H IDT2308-2 IDT2308-3 IDT2308-4 IDT2309
Contextual Info: APPLICATION NOTE AN-229 ZERO DELAY BUFFERS APPLICATION NOTE AN-229 ZERO DELAY BUFFERS WHAT IS A ZERO DELAY BUFFER? WHAT IS THE IDT2305, IDT2308 AND IDT2309? A zero delay buffer is a device that can fan out one clock signal into multiple clock signals, with zero delay and very low skew between the

Contextual Info: DATA SHEET ICS2305 ICS2305 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Description Features The ICS2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on ICS’ proprietary low jitter Phase Locked Loop PLL

IDT2305-1HDCI

Abstract: idt 2510 IDT74FCT3807 IDTQS532805 IDTQS53806 cmos cross CY7B991V-7JC
Contextual Info: Selector/Cross Reference Guide for Clock Management Products advanced Timing solutions IDT offers a complete array of timing solutions for system designers. A s a leading communications IC provider, IDT is committed to offering a complete portfolio for your timing needs. IDT’s clock

IDT2305-1HDCI

Abstract: p16c2308
Contextual Info: ADVANCED TIMING SOLUTIONS ZERO DELAY PLLs Zero Delay PLLs Zero Delay PLL replicates a single timing signal into multiple signals with What is Zero Delay PLL? virtually no delay and with low skew Input Ref Clk between the outputs. Zero Delay PLL is a high-speed phase-locked loop

49fct3805a

Abstract: 40 MHZ OSCILLATOR 49FCT805CT 5v927 74FCT88915TT70 74FCT3807D oscillator 2.048 mhz 5T9306 49FCT805BT 32 MHZ OSCILLATOR
Contextual Info: IDT Clock Management PRODUCT FAMILY and the new LVDS clock fanout family, as well as the IDT Precision and Stratum WAN PLL clock generators. Advanced Clock Management — On Time, All the Time The IDT comprehensive portfolio of Clock Management products enhances time to

KH 2222

Abstract: hp 2222 equivalent of 2222 NPN 2222 A BT2222 2222AM
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M M B T2222LT1 M M BT2222ALT1* G eneral Purpose Transistors NPN Silicon colle3ctor 'M o to ro la P referred Device 1 BASE Jl§ 2 EMITTER MAXIMUM RATINGS Rating Symbol 2222 2222A Unit C o lle c to r-E m itte r Voltage VCEO

Contextual Info: CD74FCT374 Œ BiCMOS FCT Interface Logic, Octal D-Type Flip-Flop, Three-State January 1997 Features Description • Buffered Inputs The CD74FCT374 octal D-Type, three-state, positive edge triggered flip-flop uses a small geom etry BiCMOS technol­ ogy. The output stage is a com bination of bipolar and

lm 2309

Abstract: LM308 Op Amp IC lm308h application piezoelectric transducer amplifiers
Contextual Info: u rm TECHNOLOGY LM 108A/LM308A LM108/LM308 O perational Amplifiers FCfVTURCS D € s c fu p n o n • ■ ■ ■ ■ ■ The LM 10 8 series of precision operational amplifiers are particularly well-suited for high source impedance applications requiring low offset and bias currents as

lm 2309

Abstract: LM308 application IC LM 335 piezoelectric transducer amplifiers
Contextual Info: rrw m TECHNOLOGY V L M 108A/LM308A _ LM108/LM308 Operational Amplifiers { F€flTUR€S DCSCRIPTIOn • ■ ■ ■ ■ ■ The LM108 series of precision operational amplifiers are particularly well-suited for high source impedance applications requiring low offset and bias currents as

Contextual Info: HARM S / Semiconductor BiCMOS FCT Interface Logic, Octal D-Type Flip-Flop, Three-State January 1997 Features Description • Buffered Inputs The CD74FCT374 octal D-Type, three-state, positive edge triggered flip-flop uses a small geometry BiCMOS technol­

CD74FCT374

Abstract: CD74FCT374E CD74FCT374M CD74FCT374SM
Contextual Info: CD74FCT374 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SCHS256 BiCMOS FCT Interface Logic, Octal D-Type Flip-Flop, Three-State Circuit Design • Buffered Inputs • Speed of Bipolar FAST /AS/S w • 48mA Output Sink Current

MC34081BP

Contextual Info: M C34080 thru M C34085 g MOTOROLA High Slew R ate, W ide Bandw idth, JFET Input O perational Am plifiers T h e se d e v ic e s a re a n e w g e n e ra tio n o f high sp e e d J F E T in p u t m o n o lith ic o p e ra tio n a l a m p lifie rs . In n o v a tiv e d e s ig n c o n c e p ts a lo n g w ith J F E T

34182

Abstract: 34181 34182 34181 34182P 34184P
Contextual Info: g MOTOROLA Low Power, High Slew Rate, Wide Bandwidth, JFET Input Operational Amplifiers Quality bipolar fabrication with innovative design concepts are employed for the MC33181/2/4, MC34181/2/4 series of monolithic operational amplifiers. This JFET input series of operational amplifiers operates at

Contextual Info: MOTOROLA Order this document by MTP40N10E/D SEMICONDUCTOR TECHNICAL DATA Advance Data Sheet M TP40N10E TMOS E-FET Power Field Effect Transistor N-Channel Enhancement-Mode Silicon Gate This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy

79L12

Abstract: A12L A13L A15L IDT70V9179
Contextual Info: HIGH-SPEED 3.3V 64/32K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT70V9189/79L Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12ns max.

79L12

Abstract: A12L A13L A15L IDT70V9179
Contextual Info: HIGH-SPEED 3.3V 64/32K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT70V9189/79L Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12ns max.

TTL 22pin

Abstract: 8AE20
Contextual Info: LOG IC D E V I C E S INC IbE D SSbSTDS OOQOSMb 3 L7C187 64K x 1 Static RAM T -W -Zl-oS Features Description □ 64K by 1 Static RAM with separate I/O, Chip Select power down □ Auto-Powerdown design □ Advanced CMOS technology □ High speed — to 15 ns worst-case

Contextual Info: HIGH-SPEED 3.3V 64/32K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT70V9189/79L Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12ns max.

Contextual Info: HIGH-SPEED 3.3V 64/32K x 9 IDT70V9189/79L SYNCHRONOUS PIPELINED OBSOLETE PART DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12ns max.

HY53C464LS

Abstract: LASCR HY53C464S HY53C464 MCS131 MAY94 HY53C464LF HY53C464LS70 hy53c464lf70
Contextual Info: HY53C464 Series »HYUNDAI 64K X 4-bit CMOS DRAM DESCRIPTION The HY53C464 is feist dynamic RAM organized 65,536 x 4-bit. The HY53C464 utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins to the users.

MC34002BU

Abstract: MC35002BU 34004 MC35001BU C35002
Contextual Info: MC34001, MC35001 MC34002, MC35002 MC34004, MC35004 MOTOROLA SEMICONDUCTOR TECHNICAL DATA J F E T IN P U T O P E R A T IO N A L A M P L IF IE R S Th e se lo w c o s t JF E T In p u t o p e ra tio n a l a m p lifie r s c o m b in e tw o s ta te -o f-th e -a rt lin e a r t e c h n o lo g ie s o n a s in g le m o n o lit h ic in te ­

Contextual Info: ANALOG DEVICES FEA TU RES HIGH SPE E D 50 M H z Unity Gain Stable Operation 300 V/ is Slew Rate 120 ns Settling Time Drives Unlimited Capacitive Loads High Speed, Low Power Dual Op Amp CONNECTION DIAGRAMS 8-Pin Plastic (N and Cerdip (Q) Packages 16-Pin Small Outline