24XFE Search Results

Contextual Info: PM5329 ARROW 24xFE Preview 24 Channel 10/100 Ethernet over SONET/SDH Mapping Device FEATURES • Maps up to 24 channels of full-duplex 10/100M Ethernet into 2.488 Mbps SONET/SDH. • Supports multiple encapsulation protocols for worldwide interoperability

24xFE

Abstract: PM5326 9632 PM5397
Contextual Info: PM5329 ARROW 24xFE Preliminary 24 Channel 10/100 Ethernet over SONET/SDH Mapping Device FEATURES • Maps up to 24 channels of full-duplex 10/100M Ethernet into 2.488 Mbps SONET/SDH. • Supports multiple encapsulation protocols for worldwide interoperability

Contextual Info: PM5308 TSE 120 Released PM Single Chip 74-Port STS-1/STM-0 Cross-Connect LB_IFP[4:1] rtm LBTE x4 R_P/N [26] R_P/N [27.74] LB_ECLK[4:1] RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx DMI ESSI Tx RASIO 3G Tx ESSI Tx RASIO 3G Tx ESSI Tx RASIO

Contextual Info: PM5369 TUPP 9953 Tributary Unit Payload Processor for 9953 Mbit/s 5: 49 AM Released Product Brief • Provides hardware based Message Assisted Protection Switching :1 Product Highlights • io fI Block Diagram • • 01 2 01 Low Order Processor LOPP Perf. Mon/

SDH ADM

Abstract: PM5324 PM5326 PM5370 PM5377 PM5369 extended sonet serial interface
Contextual Info: PM5369 TUPP 9953 Preliminary Tributary Unit Payload Processor for 9953 Mbit/s FEATURES • Configurable, multi-channel payload processor for aligning SONET virtual tributaries VTs or SDH tributary units (TUs) in an STS-192/STM-64 or STS-48/STM-16 data stream.

RGMII

Abstract: HSTL RGMII switch RGMII 2-channel switch SM 933 RGMII switch rgmii hstl TO lvcmos PM8363 PM8373 PM8364 24xFE
Contextual Info: PM8364 DualPHY 1GR Released 2-Channel 933 Mbit/s to 1.25 Gbit/s Transceiver FEATURES • Supports pin-programmable hardware only device configuration. • Minimal external components required. • 1.5 V and 1.8 V RGMII/RTBI interface. • 1.8 V and 2.5 V LVCMOS

Contextual Info: PM5370 WSE 40 Preliminary SONET/SDH Wideband Cross-Connect FEATURES GENERAL • Multi-purpose SONET/SDH VT/TU and SONET/SDH STS/STM cross-connect. • With a memory-switch architecture, implements a strictly non-blocking switch that supports a VT/TU level

PM5326

Abstract: PM5377 STS192 STS-48
Contextual Info: PM5377 TSE 240 Released Single Chip 96-Port STS-1/STM-0 Cross-Connect FEATURES DELAY MANAGEMENT • Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity. • 96 ingress and 96 egress STS48/STS-12 ports for a maximum of 4608 STS-1/AU-3 streams in a single

PM5326

Abstract: PM5324 PM5377 STS192 STS-48
Contextual Info: PM5377 TSE 240 Advance Single Chip 96 Port SONET/SDH Cross-Connect Switch Element FEATURES TOH PROCESSING AND TESTING • Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity. • 96 ingress and 96 egress STS48/STS-12 ports for a maximum of

MCP860

Abstract: 95L53
Contextual Info: XRT95L524 Multi-Port Ethernet MAC Aggregator Data Sheet Revision 0.5 September 20, 2007 EXAR Corporation 48720 Kato Road Fremont, CA. 94538 510 668-7000 www.exar.com Preliminary Version Copyright 2007 EXAR Corporation EXAR Corporation reserves the right to make changes to the products contained in this publication in order

PM5326

Abstract: PM5369 TUPP 9953 STM64 STS-192 STS-48 difference between oc48 oc192 PMC DM 100 108byte PM5308
Contextual Info: PM5308 TSE 120 Released AM Single Chip 74-Port STS-1/STM-0 Cross-Connect SWITCH PORT CONFIGURATION TOH PROCESSING AND TESTING LB_ID[4:1][1:0] ico R_P/N [26] ESSI Rx RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx 52 DMI DMO Memory Switch Core ESSI Tx RASIO 3G Tx ESSI Tx

OC-192/STM-64

Contextual Info: PM5308 TSE 120 Released PM Single Chip 74-Port STS-1/STM-0 Cross-Connect SWITCH PORT CONFIGURATION co LB_IFP[4:1] n LB_ID[4:1][1:0] 17 7: :0 Th BLOCK DIAGRAM LB_ED[4:1][1:0] LBTO x4 LB_EFP[4:1] LBTE (x4) LB_ICLK[4:1] er In LB_ECLK[4:1] R_P/N [26] R_P/N [27.74]

Contextual Info: PM5308 TSE 120 Released AM Single Chip 74-Port STS-1/STM-0 Cross-Connect SWITCH PORT CONFIGURATION LB_ID[4:1][1:0] 37 5: :3 LB_ED[4:1][1:0] LBTO x4 LB_EFP[4:1] LBTE (x4) LB_ECLK[4:1] rtm in LB_ICLK[4:1] er LB_IFP[4:1] of Pa R_P/N [1.25] R_P/N [26] m ea

PM5324

Abstract: PM5326 PM5369 PM5370 PM5377 PMC-2020003 PMC202 PM5369 TUPP 9953
Contextual Info: PM5369 TUPP 9953 Released Tributary Unit Payload Processor for 9953 Mbit/s FEATURES • Configurable, multi-channel payload processor for aligning SONET virtual tributaries VTs or SDH tributary units (TUs) in an STS-192/STM-64 or STS-48/STM-16 data stream.

PM5326

Abstract: SDH ADM PM5369 PM5370 PM5377 TU12 PM5370 WSE 40 PM5329 PM5324 CROSS-CONNECT
Contextual Info: PM5370 WSE 40 SONET/SDH Wideband Cross-Connect Released Product Brief Product Highlights SONET/SDH Overhead Accessibility • Multi-purpose SONET/SDH VT/TU and SONET/SDH STS/STM cross• • • • • • • • connect With a memory-switch architecture, implements a strictly nonblocking switch that supports a VT/TU level fabric of up to

PM5326

Abstract: PM5369 PM5370 PM5377 TU12
Contextual Info: PM5370 WSE 40 Preliminary SONET/SDH Wideband Cross-Connect FEATURES GENERAL • Multi-purpose SONET/SDH VT/TU and SONET/SDH STS/STM cross-connect. • With a memory-switch architecture, implements a strictly non-blocking switch that supports a VT/TU level

HSTL RGMII

Abstract: RGMII SM10B
Contextual Info: PM8364 DualPHY 1GR Released • Two independent 933 Mbit/s to 1.25 Gbits/s IEEE 802.3-2000 Gigabit Ethernet and Fibre Channel Physical Interfaces FC-PI System Compliant Transceivers. • Integrated clock synthesis, clock recovery, serializer/deserializer, builtin self-test, 8B/10B codec.

Contextual Info: PM5308 TSE 120 Released AM Single Chip 74-Port STS-1/STM-0 Cross-Connect TOH PROCESSING AND TESTING rtm LB_IFP[4:1] 51 4: LB_EFP[4:1] LBTE x4 of Pa LB_ECLK[4:1] m R_P/N [1.25] R_P/N [26] R_P/N [27.74] RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx RASIO 3G Rx

PM5326

Abstract: PM537 PM5369 PM5370 PM5377 TU12
Contextual Info: PM5370 WSE 40 Released SONET/SDH Wideband Cross-Connect FEATURES GENERAL • Multi-purpose SONET/SDH VT/TU and SONET/SDH STS/STM cross-connect. • With a memory-switch architecture, implements a strictly non-blocking switch that supports a VT/TU level fabric of up to 45 Gbit/s.

ADM processor

Abstract: PM5324 PM5369 PM5370 PM5329 PMC-2020003 TUG-3 STM16 extended sonet serial interface
Contextual Info: PM5369 TUPP 9953 Tributary Unit Payload Processor for 9953 Mbit/s Released Product Brief Product Highlights • Supports independent Line Receive and System Drop transport • Configurable, multi-channel payload processor for aligning • Supports independent transport, high-order payload and