25616 Search Results

STM32F103ZE

Abstract: STM32F10* USB Keil uVision 4 user manual microsd usb adapter keil 2 getting started with ARM Keil uVision microsd adapter usb microsoft joystick to usb
Contextual Info: www.embedinfo.com/en STM32F103ZE ARM-CM3 Board Getting Started V1.0 EMBEST CO., LTD Address: Room 509, Luohu Science & Technology Building, No.85, Taining Road, Shenzhen, Guangdong, China 518020 Telephone: 0086-755-25621715 Fax: 0086-755-25616057 Sales Email: sales.en@embedinfo.com

HYI25DC25616

Contextual Info: September 2006 HYI25 DC 25616 0 C E HYI25 DC 25680 0 C E 256 Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant Internet Data Sheet Rev. 1.00 Internet Data Sheet HYI25DC256[16/80]0CE 256 Mbit Double-Data-Rate SDRAM Revision History: Rev. 1.00, 2006-09 All

44256 ram

Abstract: 44256
Contextual Info: MITSUBISHI LSIs 25616PNA-10,-12 4194304-BIT 262144-W 0RD BY 16-BIT PSEUDO-PSEUDO STATIC RAM MODULE DESCR IPTIO N PIN C O N F IG U R A T IO N (TOP VIEW ) The M H 25616P N A is 2 6 21 4 4 word x 16 bit P S EU D O P S E U D O static R A M and consist of four industry standard

PG-VFBGA-90-3

Abstract: "ISO 2768-mK" ic hm 2007 internal block diagram ,Architecture ISO 2768 fH
Contextual Info: April 2007 HYB18M 256320 C F– 6 / 7 . 5 HYE18M 256320 C F– 6 / 7 . 5 HYB18M 256160 C F– 6 / 7 . 5 HYE18M 256160 C F– 6 / 7 . 5 DRAMs for Mobile Applications 256-Mbit Mobile-RAM Data S heet Rev.1.43 Data Sheet HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM

44256 dram

Abstract: 44256 oneDRAM 44256 ram dram 44256 16-Blt MH25616PNA-10 MH25616PNA-12 3DA7 117th
Contextual Info: M IT S U B IS H I LSIs 25616PNA-10,-12 4194304-BIT 262144-W0RD BY 16-BIT PSEUDO-PSEUDO STATIC RAM MODULE DESCRIPTION The M H 25616P N A PIN CONFIGURATION (TOP VIEW) is 2 6 2 1 4 4 w o rd x 16 b it P S E U D O - P S E U D O static R A M and consist o f fo u r in d u s try standard

ISO 2768-mk tolerances sheet

Abstract: ISO 2768-mk PG-VFBGA-90-3 HYB18M256320CF HYB18M256160CF
Contextual Info: July 2007 HYB18M 256320 C F– 6 / 7 . 5 HYE18M 256320 C F– 6 / 7 . 5 HYB18M 256160 C F– 6 / 7 . 5 HYE18M 256160 C F– 6 / 7 . 5 DRAMs for Mobile Applications 256-Mbit Mobile-RAM Internet Data Sheet Rev.1.44 Internet Data Sheet HY[B/E]18M256[16/32]0CF

Contextual Info: Internet Data Sheet, Rev. 1.40, May 2005 HYS25[L/S]256160A[F/C]–7.5 256160AC 256160AF 256MBit Mobile-RAM Mobile-RAM Commercial Temperature Range Extended Temperature Range Memory Products N e v e r s t o p t h i n k i n g . The information in this document is subject to change without notice.

Contextual Info: H B 6 6 A 2 5 6 1 6 C A - 2 5 524,288Word X 8bit /262,144Word X 16bit High Density CMOS Static RAM Card ^ H IT A C H I Rev.O sep.10,1992 T he H B 66A 25616C A -25 is a high density 5 1 2 k W o rd X 8bit o r 256kW ord X 16bit static R A M Card, m ounted o f 4pieces 1M static R A M sealed in T S O P package.

ZD-98 F

Abstract: IS61SP25616
Contextual Info: ISSI’ 25616 256K x 16 SYNCHRONOUS PIPELINED STATIC RAM A D V A N C E INFO RM ATIO N M AY 1998 FEATURES DESCRIPTION • Internal self-timed write cycle • Three chip enables for simple depth expansion and address pipelining The IS S I IS 61S P 25616 is a high-spee d, low -pow er

MH25616RNA

Abstract: MH25616RNA-15 MH25616RNA-2
Contextual Info: MITSUBISHI LSIs M H 2 5 6 1 6 R N A , - 1 5 , - 2 4 1 9 4 3 0 4 -B IT 2 6 2 1 4 4 -W O R D BY 1 6-B IT CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M H 25616R N A is 262144-word x 16-bit EPROM and consists o f fo u r industry standard 128K x 8 EPROMs and

Contextual Info: V58C2128 804/404/164 SB HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 5 6 DDR400 DDR333 7.5 ns 7.5 ns Clock Cycle Time (tCK2.5) 6ns 6 ns Clock Cycle Time (tCK3) 5ns 6 ns 200 MHz 166 MHz Clock Cycle Time (tCK2)

Contextual Info: THIS DRAWING IS UNPUBLISHED. COPYRIGHT - RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. LOC G ALL RIGHTS RESERVED. DIST R E V IS IO N S 50 LTR DESCRIPTION DATE REV PER 0 G 6 1 - 0 0 8 6 - 0 2 DWN 20DEC02 APVD JR MS D D © & @ STAMPED □N UNDERSIDE

Cyrix FasMath

Abstract: CX-83S87 cyrix 386SX fcom 7c DATA SHEET FOR OL 107 E SOLDER PEST FasMath 83D87 386SX CIRCUIT diagram 80386 83S87
Contextual Info: 83S87 User’s Manual High Performance CMOS Math Processor CYRIX CORP 3bE » H SSñ^ñn □ GQDlB'ì fi • T—49—1 2-05 FasMath CX-83S87 User's Manual January, 1990 o * P.O. Box 850118 Richardson, TX 76085-0118 CYR CYRIX CORP 3bE D ■ 2 5 ö t filici □ □ D D I M Q

dax6

Abstract: Mobile SDRAM
Contextual Info: 256164MG 256Mbit MOBILE SDRAM 1.8 VOLT, TSOP II / FBGA PACKAGE 16M X 16 75 9 10 System Frequency fCK 133 MHz 111 MHz 100MHz Clock Cycle Time (tCK3) 7.5ns 9.0 ns 10 ns Clock Access Time (tAC3) CAS Latency = 3 6.0 ns 7.0 ns 8.0ns • Available in 54-ball FBGA (with 9x6 ball array

VP271

Abstract: BC163 VP1167 VP250 bc136 vp230 General Electric CR104 BC150 BC101 DATASHEET vp251
Contextual Info: MITSUBISHI MICROCOMPUTERS M37280MFH–XXXSP, M37280MKH–XXXSP M37280EKSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 1. DESCRIPTION The M37280MFH–XXXSP and M37280MKH-XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. They

AS6UA25616

Abstract: AS6UA25616-BC
Contextual Info: October 2000 25616 2.3V to 3.6V 256Kx16 Intelliwatt low-power CMOS SRAM with one chip enable • Low power consumption: STANDBY - 72 µW max at 3.6V - 41 µW max at 2.7V • 1.2V data retention • Equal access and cycle times • Easy memory expansion with CS, OE inputs

Contextual Info: V54C365 16/80/40 4VE 64Mbit SDRAM 3.3 VOLT, TSOP II / FBGA 4M X 16, 8M X 8, 16M X 4 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns 5.4 ns

Contextual Info: V58C2512 804/404/164 SD HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 4 5 6 75 DDR500 DDR400 DDR333 DDR266 - 6ns 6ns 7.5ns 4ns 5ns - - 250 MHz 200 MHz 166 MHz 133 MHz Clock Cycle Time (tCK2.5)

Contextual Info: PRELIMINARY V59C1G01 408/808/168 QA HIGH PERFORMANCE 1Gbit DDR2 SDRAM 8 BANKS X 32Mbit X 4 (408) 8 BANKS X 16Mbit X 8 (808) 8 BANKS X 8Mbit X 16 (168) 3 25A 25 19A DDR2-667 DDR2-800 DDR2-800 DDR2-1066 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4)

Contextual Info: V58C2256 804/404/164 SA HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) 5B 5 6 7 DDR400 DDR400 DDR333 DDR266 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)

V54C3128

Contextual Info: V54C3128 16/80/40 4VB 128Mbit SDRAM 3.3 VOLT, TSOP II / FBGA 8M X 16, 16M X 8, 32M X 4 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns 5.4 ns

Contextual Info: V58C2128 804/404/164 SB HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 5 6 DDR400 DDR333 7.5 ns 7.5 ns Clock Cycle Time (tCK2.5) 6ns 6 ns Clock Cycle Time (tCK3) 5ns 6 ns 200 MHz 166 MHz Clock Cycle Time (tCK2)

Contextual Info: V54C365 16/80/40 4VE 64Mbit SDRAM 3.3 VOLT, TSOP II / FBGA 4M X 16, 8M X 8, 16M X 4 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns 5.4 ns

Contextual Info: V58C2128 804/404/164 SB HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 5B 5 6 7 DDR400 DDR400 DDR333 DDR266 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)