256KX9 Search Results

tas21a

Contextual Info: MITSUBISHI LS Is <SRAM MODULE STATIC RAM Type name 2.3i 256KX9 £ . O M BIT Max. Access time Load memory Outward dimensions Data sheet W x H x D mm) page (ns) MH25609ATN-10 10 0 M5M51008AFP x 2 + M5M5257J x 1 COMMON DATA 1 0 1 .6 x 2 4 x 5 .1 3 /9 4 /9 - 1 /9 —

L70b

Abstract: 7010K HYM5C9256
Contextual Info: H Y UN DA I E L E C T R O N I C S • SIE » j:y u h d a i SEMICONDUCTOR • Mb7SGÖfi DOODflil T37 M H Y N K HYM5C9256 256KX9-Bit CMOS DRAM MODULE M 4212 0 2 B -O C T 9 1 DESCRIPTION The HYM5C9256M is a 256K words by 9 bits dynamic RAM module and consists of nine

723653

Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide

A67P8318

Contextual Info: A67P8318/A67P7336 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM Preliminary Document Title 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History History Issue Date Remark 0.0 Initial issue July 13, 2005 Preliminary 0.1 Modify DC specification to exact value

A63P83361

Contextual Info: A63P83361 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Preliminary Document Title 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History Rev. No. 0.0 History Issue Date

A67L73361

Abstract: A67L83181
Contextual Info: A67L83181/A67L73361 Preliminary 256K X 18, 128K X 36 LVTTL, Flow-through ZeBLTM SRAM Document Title 256K X 18, 128K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue July 8, 2005 Preliminary

723653

Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide

Contextual Info: 2faE D August 6, 1990 • 05547^3 0000510 0 ■ ‘ ADVANCED ELECTRONIC PK G AEPDX256K9 DYNAMIC RAM MODULE > > 262,144 x 9 Organization > > Low 0.510 inch stand-off height > > 30 pin SIP > > Optional PARITY CHECKER on board > > Single +5V power supply > > TTL compatible

Contextual Info: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,

A67P8318

Contextual Info: A67P8318/A67P7336 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM Preliminary Document Title 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue July 13, 2005 Preliminary July, 2005, Version 0.0

CXK77920YM

Contextual Info: CXK77920TM/YM-11/12/15 262144-word x 9-bit High Speed Synchronous Static RAM Description The CXK77920TM/YM is a high speed CMOS synchronous static RAM with common l/O pins, organized as 262144-word-by-9-bit. This synchronous SRAM integrates input registers, high speed SRAM and output

A63P8336

Contextual Info: A63P8336 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Document Title 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Revision History History Issue Date Remark 0.0 Initial issue

IDT72T18105

Abstract: IDT72T18115 IDT72T18125 IDT72T1845 IDT72T1855 IDT72T1865 IDT72T1875 IDT72T1885 IDT72T1895
Contextual Info: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,

32kx18

Contextual Info: 2.5 VOLT HIGH-SPEED TeraSync FIFO PRELIMINARY IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,

Contextual Info: A67P93181/A67P83361 Preliminary 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM Document Title 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue July 12, 2005 Preliminary

Contextual Info: jot i r ’Vv SMART SM 536512 August 1991 HodularTechnoloqies R ev 1 SM536512 2MByte 512Kx36 CMOS DRAM Module General Description Features • High Density : 2Mbyte ■ Fast Access Time of 70/80/100ns (max.) ■ Low Power : 5/4.25/3.54W (max.) - Active (70/80/100ns)

723653

Abstract: 72V841 72825 72V3622 BI 7284 72V3613 723674 72V211 72V221 72V241
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’99/PC IDT FIFO Memory Products Width

256Kx1 dram pinout

Contextual Info: SM536256 August 1994 Rev 2 SMART Modular Technologies SM536256 1MByte 256K x 36 CMOS DRAM Module General Description Features The SM536256 is a high performance, 1-megabyte dynamic RAM module organized as 256K words by 36 bits, in a 72-pin, leadless, single-in-line memory module

A63L83361

Abstract: d8130
Contextual Info: A63L83361 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Document Title 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History History Issue Date Remark 0.0 Initial issue

A67L83361E

Abstract: A67L93181 A67L93181E
Contextual Info: A67L93181/A67L83361 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM Document Title 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History History Issue Date Remark 0.0 Initial issue July 13, 2005 Preliminary 0.1 Modify DC specification to exact value

BGA 144

Abstract: 208 BGA 72T3665 240-BGA 72T36125
Contextual Info: Selector Guide for TeraSync FIFOs from the leading provider of FIFO solutions • 2.5V core voltage • 225 MHz high-speed operation • Densities up to 9 M-bit • 9, 18, 36, 72-bit configurations • BGA packaging, including JTAG TeraSync the next generation

Contextual Info: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,

Contextual Info: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,

Contextual Info: A67L93181/A67L83361 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM Document Title 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History History Issue Date Remark 0.0 Initial issue July 13, 2005 Preliminary 0.1 Modify DC specification to exact value