286 BIOS Search Results

VL82c311

Abstract: VL82C1 VL82C310 VL82C310/VL82C311/VL82C311L VL82C311/VL82C311L VL82C310/VL82C311/
Contextual Info: ADVANCE INFORMATION V L S I T e c h n o lo g y , in c. VL82C310/VL82C311/VL82C311L SINGLE CHIPAT, MID-RANGE PERFORMANCE SCAMP CONTROLLER FEATURES • Fully compatible with 286- or 386SXbased PC/AT compatible systems VL82C311L is 286 compatible only • Includes:

386SX

Abstract: 82385 82385sx oti0 OTI042 OTI-040 386SX notebook 8042 controller CHIPset for 80286 Oak Frequency Control
Contextual Info: OAK TECHNOLOGY I NC SSE D • b7E^M05 G000221 b43 H O A K T ~ r-S Z -3 3 -{2 S ' Product Overview December 1991 OAK TECHNOLOGY, INC. OTI-040 286/386SX Core Logic Subsystem Features ■ ■ ■ ■ Supports 286 and 386SX CPU for 8 MHz to 25 MHz system speed.

8237 DMA

Abstract: OTI042 8042 Keyboard Controller program y803 CHIPset for 80286 oak osc 87 oscillator OTI-037
Contextual Info: OAK T E C H N O L O G Y INC SSE D • b72T4Q5 Q000221 LM3 H O A K T T -S 2 .-3 3 -& 5 ' Product Overview December 1991 OAK TECHNOLOGY, INC. OTI-040 286/386SX Core Logic Subsystem Features ■ ■ ■ ■ Supports 286 and 386SX CPU for 8 MHz to 25 MHz system speed.

386SX chipset

Abstract: OTI-020 CHIPset for 80286
Contextual Info: OAK T E C H N O L O G Y INC SSE » • b 7 2 T MD S □OGOEb'i SID « O A K T " T - 5 Z - 3 3 - Q S~ Product Overview December 1991 OAK TECHNOLOGY, INC. OTI-020 286/386SX Desktop Chip Set Features ■ Supports 286 and 386SX CPU for 8 MHz to 25 MHz system speed.

74ls612

Abstract: CHIPset for 80286 82C605 chipset 82c206 CS8221 82C206 146818 chipset 80286 ATS 16Mhz CHIPS TECHNOLOGIES
Contextual Info: ^ 2 ADVANCE INFORMATION v • - ^ /nfiSX/_ y?" 82C211, 82C212, 82C215, 82C206 CS8221: NEW ENHANCED AT/286 CHIPSet " NEAT . 9 100% IBM PC/AT Compatible New En­ hanced Chipset Supports 16MHz 80286 operation with only 0.7 wait states and 100ns DRAMs

QEMM-386

Contextual Info: by Ray Duncan Life isn't easy for the authors of commer­ cial DOS extenders these days. Their products must be capable of running on a completely standalone basis, taking full control of the 286, 386, and 486 proces­ sors in protected mode, and maintaining

zfx86bga388i

Abstract: ZFx86BGA388-c zfx86bga388-i ZFx86BGA388-c-NZ ZFx86BGA388 pc bios rom code pc motherboard check point ZF*86BGA388 ZF Micro Devices ZFx86BGA388-i-NZ
Contextual Info: ZFx86 PC-on-a-Chip  Shortest Time to Market  Faster Design Cycle  186, 286, 386 & 486 Code Compatible A True x86 "System-on-a-Chip" Regardless of the level integration, no processor is a system until it boots. The ZFx86 is the only SOC that has an internal BOOT

DS-0001-15APR2009

Abstract: ZFX86 zfx86bga388i
Contextual Info: s ude se! l c n I en Now OS lic D DR- ZFx86 PC-on-a-Chip w Shortest Time to Market w Faster Design Cycle w 186, 286, 386 & 486 Code Compatible A True x86 "System-on-a-Chip" Regardless of the level integration, no processor is a system until it boots. The ZFx86

386SX

Abstract: sd 7406 oti022 82385sx CHIPset for 80286 386sx chipset 7406 TTL 80386 chipset 8042 controller 82385
Contextual Info: OAK TECHNOLOGY INC SSE » • b72T4D5 00002^ 5 1D M O A K T "T-5Z-33- a>s~ Product Overview December 1991 OAK TECHNOLOGY, INC. OTI-020 286/386SX Desktop Chip Set Features ■ Supports 28 6 and 386SX C PU for 8 M H z to 25 M Hz sy stem speed. Reduced inventory ; same design

UM82C206

Abstract: UM82C231 V 7271 U bios phoenix
Contextual Info: UNITED MICROELECTRONICS 3QE D ^3B5&55 pooaisb q • ~ r - 9-Ò U M 8 2 C 2 3 0 Series 286 PC/AT Chip Set\ Features Pin Configurations ■ Fully PC/AT-Compatible for 10MHz and 12MHz systems ■ Guaranteed zero wait state for 80 ns DRAMs at 12MHz and one wait state for 120 ns DRAMs at 12.5 MHz

la1723

Abstract: 146818 rtc OTI-053 SA123 pca13 MC146818 OTI-054 SA11 SA21-SA23 MC146818 RTC CHIP
Contextual Info: OT1-054 1.0 INTRODUCTION TO OT1-054 ADDRESS BUFFER and REAL TIME CLOCK OTI-054 contains * 8 address buffer drivers for IBM AT or Model 30 - 286 compatible systems and replaces all the TTL address and command drivers that are norm ally required on the system board. In addition to the Address drivers. OTI-054 also includes a Real Time Clock. The Heal

f82c235

Abstract: a19t 82C765 82C235 1NTC0 LG lcd tv tuner 80286 microprocessor schematics 82C601 82c710 sues 1132
Contextual Info: 82C235 System Controller $ ' >"•' fipÉlI «V M M V // S A V A A >V * A * ^ÿV IV fWJ V ÿ . # v . . v K M ^ 0v . 4 v w v v W/ s Single CHIP 286 AT m fÊ P R E L I M I / N A R Y CH!PS* Copyright Nolle* Manual Copyright C 1991, CHIPS aad Technologies. Ine.

AADS

Contextual Info: UNITED MICROELECTRONICS 3QE D ^3B5&55 p o o a is b q • ~ r - 9-Ò U M 8 2 C 2 3 0 Series 286 PC/AT Chip Set\ Features Pin Configurations ■ Fully PC/AT-Compatible for 10MHz and 12MHz systems ■ Guaranteed zero wait state for 80 ns DRAMs at 12MHz and one wait state for 120 ns DRAMs at 12.5 MHz

Signal Path Designer

Contextual Info: OTI-055 1.0 INTRODUCTION TO OTI-055 DATA BUFFER and POWER MANAGER OTI-055 contains the data buffers for IBM AT or Model 30 - 286 compatible systems and replaces all the TTL data drivers that are normally required on the system board. In addition to the data buffers on the chip, the OTI-055 also serves as a power manager in battery-powered systems. The OTI-055 has 16

Contextual Info: JAM * 8 1931 WD7600LP CHI P SET Systems Logic fo r R A L 80386SX and 80286 KEYBOARD M O U SE PC/AT Laptop and S y s te m B lo c k D ia g r a m EPROM BIOS Notebook Compatibles ( D e v ic e s * i t h b o ld o u tlin e s a v a ila b le f r o m W e ste rn D ig ita l C o r p o r a tio n t

386D

Abstract: IR013 82340DX 386D pin configuration LM 386D 8237 DMA Controller LA23-LA17 82340
Contextual Info: AEMMKgg GK][F<0 [^RÎûÂTrD [îi] 82344 ISA BUS CONTROLLER The 82344 ISA Bus Controller replaces several of the LSI controllers used in PC/AT*-type designs with one single 160-pin quad flatpack. The Bus Controller provides the functions of DMA, page address register, timer,

4558 DX

Abstract: 8237 DMA Controller 82340DX 82340 386DX Intel 8237 dma controller block diagram 386DX bios INTEL 386DX 386TM LA17
Contextual Info: ÄiWANI ! 0iKlF O [^[jMi]ÄTD@K] 82344 ISA BUS CONTROLLER The 82344 ISA Bus Controller replaces several of the LSI controllers used in PC/AT*-type designs with one single 160-pin quad ftatpack. The Bus Controller provides the functions of DMA, page address register, timer,

nmj 4558

Abstract: 82340DX 386DX 8237 DMA Controller Intel 8237 dma controller block diagram 4558 DX 82340 19-5AO ISA bus controller INTEL 386DX
Contextual Info: 82344 ISA BUS CONTROLLER The 82344 ISA Bus Controller replaces several o f the LSI controllers used in P C /A T *-type designs with one single 160-pin quad ftatpack. The Bus C ontroller provides the functions o f DMA, page address register, timer, interrupt control, Port B logic, slot bus refresh address generation, and real time clock.

80288

Contextual Info: FE3031 WESTERN DIGITAL DATA 0:7 D ( 0:7 ) 646 í É EDATA ( 0:7 ) D ( 8:15 ) DATA (8:15) MDATA ( 0:7 ) 646 PARITY OUTPUTS PARITY INPUTS 280 646 PARITY ERROR MDATA (8:15) MEMR YMEMÏT 245 YMËMW Figure 2. FE3031 Functional Block Diagram AT Data Buffer I

386TMSX

Contextual Info: intei  D « œ i O M F @ ß [M A ¥ D M 82343 SYSTEM CONTROLLER/DATA BUFFER The 82343 contains the system control and data buffering functions in a 160-pin quad flatpack. The 82343’s functions are highly programmable via a set of internal configuration registers. Defaults on

386SX

Abstract: programming logic controller 387SX DIR245 ISA bus controller LIM EMS 4.0 "Memory Interface" AL3M
Contextual Info: EM TOR in t e i 82343 SYSTEM CONTROLLER/DATA BUFFER The 82343 contains the system control and data buffering functions in a 160-pin quad flatpack. The 82343’s functions are highly programmable via a set of internal configuration registers. Defaults on reset for the configuration registers mimic the com­

8088 assembly language manual

Abstract: intel 8086 8086 assembly language reference manual Intel 8088 programmers reference exception processing sequence 8086 Programmers Reference Manual intel 8086 opcode sheet intel Programmers Reference Manual intel 286 pic 8086 data sheet
Contextual Info: Guidelines for Writing FPU Exception Handlers 35 As described in “Floating-Point Unit”, the Intel Architecture supports two mechanisms for accessing exception handlers to handle unmasked FPU exceptions: native mode and MS-DOS compatibility mode. The primary purpose of this appendix is to provide detailed information to

fe3031

Abstract: 74lsxxx 80286 DMA ic 80286
Contextual Info: FE3031 INTRODUCTION 1.0 INTRODUCTION 1.1 DESCRIPTION 1.2 The FE3031 is an IBM* AT data buffer and parity generator/checker in a 100-pin PLCC package that contains all of the data buffers necessary to im plem ent an AT com patible computer. The FE3031 functions as a peripheral data bus buffer,

ISO 14229

Abstract: 82340SX 82340DX 32C54 8254 AA 74LSI12 Ba 33 bco sp m04w SPICE QT 44 CIRCUIT DIAGRAMS UAA 1250
Contextual Info: ov '> i WM' ADVANCED _ 82344 ISA BU S CO N TR O LLER DESCRIPTION The 82344 ISA Bus C ontroller replaces several of the LSI controllers used in PC/AT-type deaigna w ith ona single 160-pin quad ftapacfc. Tha Bus ControUar providee the functicna of