2MX1 Search Results

CMS3216LAF

Abstract: CMS3216LAG CMS3216LAH
Contextual Info: CMS3216LAx-75xx 32M 2Mx16 Low Power SDRAM Revision 0.2 January, 2007 Rev0.2, Jan. 2007 CMS3216LAx-75xx Document Title 32M(2Mx16) Low Power SDRAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft Mar.3rd, 2005 Preliminary 0.1 Add H(Pb-Free & Halogen Free) descriptions

K7A323600M

Abstract: K7B321825M-QC65 K7A321800M
Contextual Info: K7A323600M K7A321800M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

K7M321825M

Abstract: K7M321825M-QC75 K7M323625M K7M323625M-QC75
Contextual Info: K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Preliminary 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

K1S3216B1C-FI70

Abstract: K1S3216B1C K1S3216B1C-I
Contextual Info: Preliminary K1S3216B1C UtRAM Document Title 2Mx16 bit Uni-Transistor Random Access Memory Revision History Revision No. History Draft Date Remark 0.0 Initial Draft January 16, 2003 Advanced 0.1 Revised - Changed Package Type from 48 TBGA into 48 FBGA 6.0 x 8.0

K7M321825M

Abstract: K7M323625M
Contextual Info: K7M323625M K7M321825M Preliminary 1Mx36 & 2Mx18 Flow-Through NtRAM TM 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM FEATURES GENERAL DESCRIPTION • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O

WS1M32V-XG3X

Contextual Info: White Electronic Designs WS1M32V-XG3X PRELIMINARY* 1Mx32 SRAM 3.3V MODULE FEATURES Access Times of 17, 20, 25ns 3.3V Power Supply 84 lead, 28mm CQFP, Package 511 Low Power CMOS Organized as two banks of 512Kx32, User Configurable as 2Mx16 or 4Mx8 Built-in Decoupling Caps and Multiple Ground Pins

MASK ROM 32M PROGRAM

Abstract: K3N6C4000E-DC mask rom A2034
Contextual Info: K3N6C4000E-DC CMOS MASK ROM 32M-Bit 2Mx16 CMOS MASK ROM FEATURES GENERAL DESCRIPTION • 2,097,152x16 bit organization • Fast access time 100ns(Max.) : CL=50pF 120ns(Max.) : CL=100pF • Supply voltage : single +5V • Current consumption Operating : 50mA(Max.)

A94-10

Abstract: 4000E
Contextual Info: K3N6V U 4000E-DC CMOS MASK ROM 32M-Bit (2Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • 2,097,152x16 bit organization • Fast access time 3.3V Operation : 100ns(Max.)@CL=50pF, 120ns(Max.)@CL=100pF 3.0V Operation : 120ns(Max.)@CL=100pF • Supply voltage : single +3.0V/ single +3.3V

Contextual Info: K7P323674C K7P321874C 1Mx36 & 2Mx18 SRAM 36Mb Late Write SRAM Specification 119BGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: Advance K1S321615C UtRAM Document Title 2Mx16 bit Uni-Transistor Random Access Memory Revision History Revision No. History 0.0 Initial Draft Draft Date Remark April 18, 2003 Advanced The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

Contextual Info: WS1M32V-XG3X PRELIMINARY* 1Mx32 SRAM 3.3V MODULE FEATURES  Access Times of 17, 20, 25ns  3.3V Power Supply  84 lead, 28mm CQFP, Package 511  Low Power CMOS  Organized as two banks of 512Kx32, User Configurable as 2Mx16 or 4Mx8

F2M1

Contextual Info: !. es 2Mx16 5V FLASH MODULE W F 2 M 1 6 -X X X 5 ADVANCED1 FEATURES • Access Time of 9 0 ,1 2 0 ,150ns Low Po w er C M O S ■ Packaging: Data Polling and Toggle Bit feature for detection of program or erase cycle completion. • 66-pin, PGA Type, 1.185 inch square, Herm etic Ceramic

Contextual Info: a WF1M 32B-XXX5 WHITE /MICROELECTRONICS 1Mx325V/12V FLASH MODULE PRELIMINAR/* FEATURES • Access Times of 100,120ns Organized as 1Mx32, user configurable as 2Mx16 or4Mx8. ■ Commercial, Industrial and Military Temperature Ranges Packaging: • 66-pin, PGA Type, 1.185 inch square, Hermetic

SAMSUNG MCP

Abstract: samsung K5 MCP BA35 BA4110 ba4410 BA651 Flash Memory SAMSUNG k5
Contextual Info: Preliminary MCP MEMORY K5A3x40YT B B Document Title Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM Revision History Revision No. History 0.0 Initial Draft Draft Date Remark February 22, 2002 Preliminary

Contextual Info: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: K7Q323684M K7Q321884M 1Mx36 & 2Mx18 Preliminary b4 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. September 5, 2001 Advance 0.1 1. Changed Pin configuration at x36 organization.

WS1M32V-XG3X

Contextual Info: White Electronic Designs WS1M32V-XG3X PRELIMINARY* 1Mx32 SRAM 3.3V MODULE FEATURES Access Times of 17, 20, 25ns 3.3V Power Supply 84 lead, 28mm CQFP, Package 511 Low Power CMOS Organized as two banks of 512Kx32, User Configurable as 2Mx16 or 4Mx8 Built-in Decoupling Caps and Multiple Ground Pins

Contextual Info: K7Q323682M K7Q321882M 1Mx36 & 2Mx18 Preliminary b2 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. September, 5 2001 Advance 0.1 1. Changed Pin configuration at x36 organization.

WEDF1M32B-XXX5

Abstract: WEDF1M32B-XG2TX5 WEDF1M32B-XHX5 1m 0880
Contextual Info: White Electronic Designs WEDF1M32B-XXX5 ADVANCED* 1Mx32 5V Flash Module FEATURES Access Times of 70, 90, 120ns Packaging: Organized as 1Mx32, user configurable as 2Mx16 or 4Mx8. • 66 pin, PGA Type, 1.185” square, Hermetic Ceramic HIP Package 401 Commercial, Industrial and Military Temperature

jedec ms-024

Abstract: MS-024-FA ms024 WED416S8030A-S 2Mx16bit
Contextual Info: White Electronic Designs WED416S8030A-SI 2Mx16x 4 Banks Synchronous DRAM FEATURES DESCRIPTION Single 3.3V power supply The WED416S8030AxxSI is 134,217,728 bits of synchronous high data rate DRAM organized as 4 x 2,097, 152 words x 16 bits. Synchronous design allows

Contextual Info: K7R323684C K7R321884C K7R320984C Preliminary TM 1Mx36, 2Mx18 & 4Mx9 QDR II b4 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

mask rom

Contextual Info: KM23V32005D E TY/KM23S32005D(E)TY CMOS MASK ROM 32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 4,194,304x8(byte mode) 2,097,152x16(word mode) • Fast access time Random Access Time/Page Access Time 3.3V/3.0V Operation : 100/30ns(Max.)

Contextual Info: KM23V32000D E TY/KM23S32000D(E)TY CMOS MASK ROM 32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 4,194,304x8(byte mode) 2,097,152x16(word mode) • Fast access time Random Access Time 3.3V/3.0V Operation : 100ns(Max.)

Contextual Info: KM23C32000C E T CMOS MASK ROM 32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 4,194,304x8(byte mode) 2,097,152x16(word mode) • Fast access time : 100ns(Max.) • Supply voltage : single +5V • Current consumption