2MX16 EEPROM Search Results
2MX16 EEPROM Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| X28C512DM-15/B |
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X28C512 - EEPROM, 64KX8, Parallel, CMOS |
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| X28C512JI-15 |
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X28C512 - EEPROM, 64KX8, 150ns, Parallel, CMOS, PQCC32 |
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| X28C512JI-12 |
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X28C512 - EEPROM, 64KX8, 120ns, Parallel, CMOS, PQCC32 |
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| X28C512DM-15 |
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X28C512 - EEPROM, 64KX8, 150ns, Parallel, CMOS, CDIP32 |
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| X28C010FI-15 |
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X28C010 - EEPROM, 128KX8, 150ns, Parallel, CMOS, CDFP32 |
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2MX16 EEPROM Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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DP5Z2MW16PA3
Abstract: DP5Z2MW16PH3 DP5Z2MW16PI3 DP5Z2MW16PJ3 DP5Z2MW16PY3
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2Mx16, 200ns, 30A161-22 DP5Z2MW16Pn3 50-pin 64-Megabits DP5Z2MW16Pn3 DP5Z2MW16PA3 DP5Z2MW16PH3 DP5Z2MW16PI3 DP5Z2MW16PJ3 DP5Z2MW16PY3 | |
DP5Z2ME16PA3
Abstract: DP5Z2ME16PH3 DP5Z2ME16PI3 DP5Z2ME16PJ3 DP5Z2ME16PY
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2Mx16, 200ns, 30A161-02 DP5Z2ME16Pn3 50-pin 32-Megabits DP5Z2ME16PY DP5Z2ME16Pn3 30A161-42 DP5Z2ME16PA3 DP5Z2ME16PH3 DP5Z2ME16PI3 DP5Z2ME16PJ3 DP5Z2ME16PY | |
DP5Z2MK16PA3
Abstract: DP5Z2MK16PH3 DP5Z2MK16PI3 DP5Z2MK16PJ3 DP5Z2MK16PY
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2Mx16, 200ns, 30A161-02 DP5Z2MK16Pn3 DP5Z2MK16n3 50-pin 32-Megabits DP5Z2MK16PY DP5Z2MK16Pn3 30A161-32 DP5Z2MK16PA3 DP5Z2MK16PH3 DP5Z2MK16PI3 DP5Z2MK16PJ3 DP5Z2MK16PY | |
SLCC Series
Abstract: DP5Z2MX16PA3 DP5Z2MX16PH3 DP5Z2MX16PI3 DP5Z2MX16PJ3 DP5Z2MX16PY
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2Mx16, 200ns, 30A161-02 DP5Z2MX16Pn3 50-pin 32-Megabits DP5Z2MX16PY DP5Z2MX16Pn3 DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3 SLCC Series DP5Z2MX16PA3 DP5Z2MX16PH3 DP5Z2MX16PI3 DP5Z2MX16PJ3 DP5Z2MX16PY | |
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Contextual Info: 4Mx8/2Mx16/1Mx32, 90 - 120ns, PGA 30A126-22 D 32 Megabit FLASH EEPROM DPZ1MH32NV3 DESCRIPTION: The DPZ1MH32NV3 ‘’VERSA-STACK’’ module is a revolutionary new memory subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip Carriers SLCC mounted on a co-fired ceramic substrate. It offers |
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4Mx8/2Mx16/1Mx32, 120ns, 30A126-22 DPZ1MH32NV3 DPZ1MH32NV3 | |
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Contextual Info: 4Mx8/2Mx16/1Mx8, 90 - 120ns, PGA 30A126-02 F 32 Megabit FLASH EEPROM DPZ1MX32NV3 DESCRIPTION: The DPZ1MX32NV3 ‘’VERSA-STACK’’ module is a revolutionary new memory subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip Carriers SLCC mounted on a co-fired ceramic substrate. It offers 32 |
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4Mx8/2Mx16/1Mx8, 120ns, 30A126-02 DPZ1MX32NV3 DPZ1MX32NV3 | |
M25P08
Abstract: MD2800-D08 pmc flash pm49fl004t-33jc MD2810-D08 m25p04 SDTB-128 MD2811-D32-V3 M25P08-V-MN-6-T Sandisk TSOP EPROM databook am27c256 120
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SST39SF512; SST29EE512 AM28F512 M29F512 AT49F512, AT29C512 W29EE512 SST39SF010; SST29EE010 AM29F010, M25P08 MD2800-D08 pmc flash pm49fl004t-33jc MD2810-D08 m25p04 SDTB-128 MD2811-D32-V3 M25P08-V-MN-6-T Sandisk TSOP EPROM databook am27c256 120 | |
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Contextual Info: SM56404807UNWUU Preliminary Revision History • May 9, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • August 31, 1998 Preliminary datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com |
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SM56404807UNWUU 32MByte | |
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Contextual Info: SM56404807UX6UU Preliminary B Revision History • May 31, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • May 29, 1998 Preliminary datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com |
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SM56404807UX6UU 32MByte | |
DP5ZContextual Info: n INDEX GENERAL PRODUCT INFORMATION Dense-Pac Memory Module and Monolithic E merging T echnology / Products. Quality and R e lia b ilit y . Warranty . . 6 . 7 . 8 14 SRAM PRODUCTS |
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128Kx8, 64Kx16, 256Kx8, 384Kx8, DP5Z | |
SST25VF128
Abstract: SST25VF128C soic-8 200mil TSOP32 FOOTPRINT footprint WSON-8 SST12LP15A TSOP32 8 X 14 FOOTPRINT BIOS 32 Pin SST39SF040 SST25VF080B BIOS electronic clock on breadboard
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Contextual Info: January 1997 Revision 2.0 DATASHEET SDC2UV6482 A -(67/84/100/125) T-S 16MByte (2Mx 64) CMOS Synchronous DRAM Module General Description The SDC2UV6482(A)-(67/84/100/125)T-S is a high performance, 16-megabtye synchronous, dynamic RAM module organized as 2M words by 64 bits, in a 168-pin, dual-in-line memory module (DIMM) package. |
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SDC2UV6482 16MByte 16-megabtye 168-pin, MB81117822A- 125MHz) V6482 168-pin | |
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Contextual Info: SM57204807UE6UU Preliminary B Revision History • May 31, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • May 29, 1998 Preliminary datasheet released. Note* : |
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SM57204807UE6UU A10/AP 32EREIN | |
JEP-106EContextual Info: July 1997 Revision 1.0 data sheet SDC3UV6482- 67/84/100/125 T-S 24MByte (3M x 64) CMOS Synchronous DRAM Module General Description The SDC3UV6482-(67/84/100/125)T-S is a high performance, 24-megabtye synchronous, dynamic RAM module organized as 3M words by 64 bits, in a 168-pin, dual-in-line memory module (DIMM) package. |
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SDC3UV6482- 24MByte 24-megabtye 168-pin, MB81117822A- MB811171622A- 1Mx16 MP-DRAMM-DS-20539-7/97 JEP-106E | |
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Contextual Info: SM564067574N6UP May 23, 2000 Revision History • May 23, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • January 6, 2000 Modified module length from 133.37mm to 133.35mm. |
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SM564067574N6UP SM564067574N6BP SM564067574N6UP. | |
SM2M64SDTGREYEContextual Info: SM2M64SDTGREYE May 22, 2000 Revision History • May 22, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • May 13, 1998 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com |
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SM2M64SDTGREYE 16MByte SM2M64SDTGREYE | |
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Contextual Info: SM56402807UX6UU Preliminary B Revision History • May 31, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • May 29, 1998 Preliminary datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com |
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SM56402807UX6UU 16MByte | |
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Contextual Info: SM56402807UNWUU May 3, 2001 Revision History • May 3, 2001 Modified datasheet. • May 9, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • August 31, 1998 |
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SM56402807UNWUU | |
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Contextual Info: cP FUJI October 1996 Revision 1.0 DATA SHEET - ' EDC4U V7282- 60/70 (J/T)G-S 32MByte (4M x 72) CMOS EDO DRAM Module - 3.3V (ECC) General Description The EDC4UV7282-(60/70)(J/T)G -S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module orga |
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V7282- 32MByte EDC4UV7282- 32-megabyte 168-pins, B81V17805A- 168-pin | |
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Contextual Info: January 1997 Revision 3.0 D A T A S H E E T - SDC2UV7282 A -(67/84/100/125)T-S 16MByte (2M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC2UV7282(A)-(67/84/100/125)T-S is a high performance, 16-megabtye synchronous, dynamic RAM module organized |
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SDC2UV7282 16MByte 16-megabtye 168-pin, MB81117822A- V7282 168-pin SDC2UV7282) | |
2MX16Contextual Info: October 1996 Revision 1.0 DATA SHEET EDC4UV7282- 60/70 (J/T)G-S 32MByte (4M x 72) CMOS EDO DRAM Module - 3.3V (ECC) General Description The EDC4UV7282-(60/70)(J/T)G-S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module organized as 4M words by 72 bits, in a 168-pins, dual-in-line (DIMM) memory module with ECC. |
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EDC4UV7282- 32MByte 32-megabyte 168-pins, MB81V17805A- 32MBormation MP-DRAMM-DS-20416-10/96 2MX16 | |
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Contextual Info: cP ÏITSIJ I A M. July 1997 Revision 1.0 data sheet EDC4UV7282B-60 J/T G-S 32MByte (4M x 72) CMOS EDO DRAM Module -3.3V (ECC) General Description The EDC4UV7282B-60(J/T)G-S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module organized |
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EDC4UV7282B-60 32MByte 32-megabyte 168-pin, MB81V17805B-60 72-pin 144-pin 168-pin 200-pin | |
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Contextual Info: SM56403707UN6BU May 22, 2000 Revision History • May 22, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • November 25, 1998 Changed datasheet part no. from SM56403707UN6UU to SM56403707UN6BU. |
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SM56403707UN6BU SM56403707UN6UU SM56403707UN6BU. | |
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Contextual Info: January 1997 Revision 2.0 D A TA SH EET - SOB2UV6482- 67/84/100/125 T-S 16MByte (2Mx 64) CMOS Synchronous DRAM Module General Description The SOB2llV6482-(67/84/100/125)T-S is a high performance, 16-megabtye synchronous, dynamic RAM module organized as |
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SOB2UV6482- 16MByte SOB2llV6482- 16-megabtye 144-pin, MB81117822A- 200mV. V6482- 144-pin | |