30 LVDS Search Results

Contextual Info: SCAN921025,SCAN921226 SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 JTAG and at-speed BIST Literature Number: SNLS148B OBSOLETE October 24, 2011 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with

XC3S50AN

Abstract: XC3S700AN xc3s200an FTG256 616 xc3s200an user FGG484 Spartan-3an xc3s50an spartan3an DS557 XC3S400AN
Contextual Info: 1 Spartan-3AN FPGA Family Data Sheet DS557 November 30, 2010 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS557 v4.0 November 30, 2010 DS557 (v4.0) November 30, 2010 • • • • •

Contextual Info: DS92LV1224 DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer Literature Number: SNLS189 DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer General Description Features The DS92LV1224 is a 300 to 660 Mb/s deserializer for high-speed unidirectional serial data transmission over FR-4

Contextual Info: DS92LV1023E DS92LV1023E 30-66 MHz 10 Bit Bus LVDS Serializer Literature Number: SNLS187A DS92LV1023E 30-66 MHz 10 Bit Bus LVDS Serializer General Description Features The DS92LV1023E is a 300 to 660 Mb/s serializer for highspeed unidirectional serial data transmission over FR-4

Contextual Info: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

62162

Abstract: 62161 LVDS scsi cable VHDCI 36 dura amp 82068 amp champ 636217-1
Contextual Info: VHDCI; Ultra-SCSI; LVDS; SCI CHAMP 0.8 mm High Density Cable Assemblies Catalog 296531 issued n ge • High density, low profile, 0.8 mm connectors ■ Fully shielded interconnect ■ IDC terminations ■ #30 AWG solid or stranded twisted pair cable ■ #30 AWG shielded differen­

MO-150

Abstract: SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023 SN65LVDS1224
Contextual Info: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

ATM machine working circuit diagram

Abstract: gearbox 405 Virtex-II Pro xc2vp50ff1152 Virtex-II Pro xc2vp70ff1517 K162 Virtex-II 250v ACE 69 D37 connector pcb IBM Processor Local Bus (PLB) 64-Bit Architecture R 2.8 no pinout 4
Contextual Info: 1 R DS083 v4.0 June 30, 2004 Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet Product Specification Module 1: Introduction and Overview Module 3: DC and Switching Characteristics DS083-1 (v4.0) June 30, 2004 9 pages DS083-3 (v4.0) June 30, 2004

Contextual Info: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

P611-30

Contextual Info: PL611-30 Programmable Quick Turn Clock FEATURES PIN CONFIGURATION XIN, FIN 1 GND 2 CLK0 3 CLK1 4 PL611-30 • Advanced programmable PLL design • Very low Jitter and Phase Noise < 40ps Pk-Pk typ. • Supports complementary LVCMOS outputs to drive LVPECL and LVDS inputs.

the pll 2002

Contextual Info: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527E – FEBRUARY 2002 – REVISED SEPTEMBER 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

P611-30

Contextual Info: PL611-30 Programmable Clock FEATURES PIN CONFIGURATION XIN, FIN 1 GND 2 CLK0 K CLK1 3 4 PL611-30 • Advanced programmable PLL design  Very low Jitter and Phase Noise < 40ps Pk -Pk typ.  Supports complementary LVCMOS outputs to drive LVPECL and LVDS inputs.

Contextual Info: DS92LV1224 www.ti.com SNLS189 – APRIL 2005 DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer Check for Samples: DS92LV1224 FEATURES • 1 • 23 • • • 30–66 MHz Single 1:10 Deserializer with 300–660 Mb/s troughput Robust Bus LVDS serial data transmission

Contextual Info: SN65LV1023/SN65LV1224 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527A – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

SN65LVDS1023

Abstract: SN65LVDS1023DB SN65LVDS1224 SN65LVDS1224DB
Contextual Info: SN65LVDS1023/SN65LVDS1224 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527 – FEBRUARY 2002 D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224 Chipset Serializer/Deserializer Power

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527H – FEBRUARY 2002 – REVISED FEBRUARY 2007 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527H – FEBRUARY 2002 – REVISED FEBRUARY 2007 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527H – FEBRUARY 2002 – REVISED FEBRUARY 2007 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

pecl logic voltage levels

Abstract: VAAC Emitter Coupled Logic resistor Network
Contextual Info: Application Brief 30

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527G – FEBRUARY 2002 – REVISED JANUARY 2005 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527H – FEBRUARY 2002 – REVISED FEBRUARY 2007 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527G – FEBRUARY 2002 – REVISED JANUARY 2005 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224† 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527C – FEBRUARY 2002 – REVISED MAY 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224