300MLL Search Results

Contextual Info: Plastic sm all outline J-bend SO J 20/26-pln 300mll Min Max A 0.140 Al 0.020 A2 0.095 0.105 E 0.025 0.032 b 0.016 0.022 c 0.008 0.014 D 0.686 I 0.245 0.285 El 0.295 0.305 E2 0.327 0.347 e 0.050 BSC Dimensions In Inches 24/26-pin 300 mil Min Max 0,148 0.026 0.106 NOM

IR 30 D1

Contextual Info: SN74ALS236 64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107A-OCTOBER 1986 - REVISED SEPTEMBER 1993 Asynchronous Operation Organized as 64 Words by 4 Bits DW OR N PACKAGE TOP VIEW r NC [ 1 Data Rates From 0 to 30 MHz 3-State Outputs 16 J VCC 15 ] S O

Contextual Info: SN54ALS05A, SN74ALS05A HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS S D A S 1 9 0 A - APRIL 1982 - R EVISED DECEMBER 1994 Package Options Include Plastic Small-Outllne D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mll DIPs

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: SN54ALS29823, SN74ALS29823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS S D A S 1 4 6 B -J A N U A R Y 198« - R EVISED JANUARY 1995 Functionally Equivalent to AMD’s AM29823 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With

Contextual Info: SN54ALS1034, SN54AS1034A, SN74ALS1034, SN74AS1034A HEX DRIVERS SDAS063B - APRIL 19S2 - REVISED JANUARY 1995 'AS1034A Offer High Capacltlve-Dri ve Capability Noninverting Drivers Package Options Include Plastic Small-Outllne D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and

Contextual Info: SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS034B - DECEMBER 1982 - REVISED JANUARY 1996 • • • • • Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HCOO

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

bd 9d

Abstract: SN74ALS29841
Contextual Info: SN74ALS29841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS S D A S 1 4 9 A - JU N E 1 9 8 8 - REVISED JA N U A R Y 1995 3-State Buffer-Type Outputs Drive Bus Lines Directly DW OR NT PACKAGE TOP VIEW Bus-Structured Pinout m Provides Extra Bus-Driving Latches

Contextual Info: SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3CAS317A- NOVEMBER 1993 - REVISED OCTOBER 199S | • Member of the Texas Instruments Wldobua Family • EP/C™ Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce)

Contextual Info: SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR S D A S 2 1 8 A -A P R IL 1982 - REVISED DECEMBER 1994 SN54ALS273 . . . J PACKAGE SN74ALS273. . . DW OR N PACKAGE TOP VIEW Contain Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct-Clear inputs

Contextual Info: SN54BCT2828B, SN74BCT2828B 10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE INVERTING OUTPUTS _ D3635, SEPTEMBER 1990 S N 54B C T282B B . . . J T P A C K A G E BiCMOS Design Substantially Reduces S N 7 4B C T 28 2 8B . . . D W O R N T P A C K A G E

74as74

Contextual Info: SN74ALS74A, SN74AS74, SN54ALS74A, SN54AS74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2M 1, APRIL 1982 - REVISED SEPTEM BER 1987 Package Options Includa Plaatlc "Sm a ll OutHna" Package!, Ceramlc Chip Carrlara. and Standard Plattlc and Caramic 300-mll

74AC11827

Contextual Info: 54AC11827, 74AC11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0155— 0 3 3 7 9 . NOVEMBER 1989— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54AC11827 . . . JT PACKAGE 74AC11827 . . . DW OR NT PACKAGE TOP VIEW

Contextual Info: SN54HC03, SN74HC03 QUADRUPLE 2-INPUT POSITIVE-NAMD GATES WITH OPEN-DRAIN OUTPUTS _ Package Options Include Plastic Small-Outllne D and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mll DIPs

SN54LV14

Abstract: 2020CN
Contextual Info: SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS _ S C L S 1 8 7 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-|i Process SN54LV14 . . . J OR W PACKAGE SN74LV14. . . D, DB, OR PW PACKAGE (TOP VIEW) TVplcal V q l p (Output Ground Bounce)

Contextual Info: SN54F11, SN74F11 TRIPLE 3-INPUT POSITIVE-ANO GATES D2932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mll DIPs SN64F11 . . . J PACKAGE SN74F11 . . . D OR N PACKAGE

Contextual Info: SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS _S C L S 1 7 9 A - MARCH 1 9 6 4 - REVISED JANUARY 1906 • Inputs Are TTL-Voltage Compatible • Independent Registers and Enables for A and B Buses •

Contextual Info: 74ACT11132 QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS SCAS177 - D3974, JANUARY 1992 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Center-Pin V^c and GND Pin Configurations Minimize High-Speed Switching Noise EP/C Enhanced-Performance Implanted

Contextual Info: SN74ALS229B 16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SPAS09Q - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs • 16 Words by 5 Bits • Data Rates From 0 to 40 MHz • Fall-Through Time. . . 14 ns "typ • 3-State Outputs

Contextual Info: SN74AS353B DUAL 1-0F-4 DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS ^ _ SD A S2 2 2 A -A P R IL 1982 - REVISED D ECEM BER 1994 • Inverting Version of 'AS253 • Permits Multiplexing From n Lines to One Line • Performs Parallel-to-Serlal Conversion

Contextual Info: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [

Contextual Info: SN74AS7S6, SN74AS757 SN54AS7S6 OCTAL BUFFERS AND UNE DRIVERS WITH OPEN-COLLECTOR OUTPUTS D2661, DECEM BER 1983 - REVISED FEBRUA RY IM S • Open-Collector Outputs Drive But Line* or Buffer Memory Addreu Register • Eliminates the Need for 3-State Overlap

Contextual Info: SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069S- NOVEMBER 198« - REVISED MARCH 1996 • ■ I • • Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers I I •