31812 Search Results

Contextual Info: 31812 Product Details - Tyco Electronics Electronic Components | Segments | Who We Are Corporate Home | Products Page 1 of 2 Documentation Resources My Account Customer Support 31812 Product Details Ring and Spade Tongue Terminals Previous 1 [2] 3 4 5 . 20 Next

Contextual Info: CY7C1163KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports

Contextual Info: CY7C1243KV18/CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:

Contextual Info: SM www.vishay.com Vishay Huntington Wirewound Resistors, Precision Power, Surface Mount FEATURES • All welded construction • Molded encapsulation • Wraparound terminations • Excellent stability at different environmental conditions • High power ratings up to 4 W

Solistrand 65505

Abstract: tyco 30692 E13288 m7928 7 AMP 59973-1 crimper MS20659 M7928/7 MIL-T-7928g 74909 m 52707
Contextual Info: SOLISTRAND, Budget and DIAMOND GRIP Uninsulated Terminals and Splices Catalog 65505 Revised 9-00 Product Facts • SOLISTRAND Terminals and Splices ■ Utilize a brazed seam ■ Applied with “W” crimp tooling ■ Available in wire sizes 26 AWG – 600 MCM

NS250H

Abstract: NS160H NSX100H Schneider NSX 400 F NS100N NS100H MA NS250N NSX100 NS160N NSX100F
Contextual Info: Low Voltage Compact NSX100 to 630 Circuit breakers and switch-disconnectors Substitution guide - Technical characteristics 2010 Substitution guide Technical characteristics Performance levels and trip units 2 Compact NS100/160/250 Compact NSX100/160/250 Compact NS400/630

2-34119-1

Contextual Info: SOLISTRAND, Budget and DIAMOND GRIP Uninsulated Terminals and Splices Catalog 65505 Revised 9-00 Ring Tongue Terminals Wire Size Range AWG 26 to 16, CMA 202 to 3,260 [0.1 to 1.65 mm2] Material Terminal Body — Copper per ASTM B-152 Plating — Tin per MIL-T-10727

MS20659

Abstract: E13288 LR7189
Contextual Info: 4 T H IS D R A W IN G IS 3 U N P U B L IS H E D . R ELEASED FO R A LL C O P Y R IG H T BY TYCO E L E C T R O N IC S P U B L IC A T IO N N TE R N A TIO N A L RIGHTS 2 , - LOC R E S E R VE D . R E V IS IO N S D IS T G C O R P O R A T IO N . D E S C R IP T IO N

3M Touch Systems

Contextual Info: CY7C1168KV18, CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.5 cycles:

SKIIP 33 nec 125 t2

Abstract: skiip 613 gb 123 ct RBS 6302 ericsson SKIIP 513 gb 173 ct THERMISTOR ml TDK 150M pioneer PAL 010a Project Report of smoke alarm using IC 555 doc SKiip 83 EC 125 T1 ericsson RBS 6000 series INSTALLATION MANUAL Ericsson Installation guide for RBS 6302
Contextual Info: Discontinued and Superseded Stock Number History. This document contains Discontinued and Superseded Stock Number History. The information is listed in the following format: Stock Number: The original RS Stock Number of the item. Brief Description: The Invoice Description of the item.

Contextual Info: CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.0 Cycles:

Contextual Info: CY7C1243KV18, CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Configurations Features Separate independent read and write data ports ❐ Supports concurrent transactions

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

25.161.0253

Abstract: A 69157 J01001A1944 69157 69157-102 Amplifier ADS AWG2021 Telegartner AD8002 AD8018
Contextual Info: AD8018 Evaluation Board EVAL-AD8018EB BOARD DESCRIPTION The AD8018 evaluation board circuit offers the ability to evaluate the AD8018 in a typical xDSL bridge hybrid circuit Figure 4 . The receiver circuit on these boards is typically unpopulated. Requesting samples of the AD8022AR with the AD8018ARUEVAL board will provide the capability to evaluate the

CY7C1245KV18-400BZXI

Abstract: 3M Touch Systems
Contextual Info: CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports

3M Touch Systems

Contextual Info: CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)

raychem catalog termination kit and splicing kit

Abstract: Raychem installation procedure rcps-200-20 raychem AD-1377 M7928/1 MS25036 raychem AD-1377 calibration NAS1745 raychem AD-1377 drawings raychem termination kit and splicing kit RBK-ILS-processor
Contextual Info: Terminals and Splices Table of Contents How to Compute Circular Mil Area of Various Wire Shapes . . . . . . . . . . . . . . . . . . . . . . 9003 Terminal Stud Hole Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9004

2-321298-6

Abstract: 2-34111-3 320383 324001-1 34118 321867 322870 322996 34119 BELL MOUTH
Contextual Info: Data downloaded from http://www.anglia.com - the website of Anglia - tel: 01945 474747 Catalogue 1654741 SOLISTRAND, Uninsulated Terminals and Splices Revised 1-04 The SOLISTRAND Terminal SOLISTRAND terminals and splices are specially designed to terminate solid and

BACC47EF1

Abstract: BACC47 BACC66 TRI-STAR BACC47EG1 BACC47EF3 BACC47EG BACC47EF2 arinc 600 coax pin size 8 317-2222-301
Contextual Info: ARINC 404 Types: • Environmental • Non-Environmental Shell Configurations: • Plug / Receptacle Pin or Socket S One Gang, type “A” Shell S One Gang, type “B” Shell S Two Gang, type “B” shell S Three Gang, type “B” shell S Four Gang, type “B” shell

intel e5300

Abstract: E5300 E6500 06F2h HH80557PG0331M Pentium E6500 06FD 06FDh pentium 06f2 Pentium Processors
Contextual Info: Product Brief Intel Pentium® Processors Embedded Computing Intel® Pentium® Processors E6500, E5300, and E2160 for Embedded Computing Product Overview Intel® Pentium® processors include the innovative features of Intel® Core microarchitecture to deliver energy-efficient dualcore performance for cost-sensitive embedded designs. Available in

intel 965gm

Abstract: 965gm Processor T2310 T2330 CK410M T2310 316273 940GML 3162* intel 3165* intel
Contextual Info: Intel Pentium® Dual-Core Mobile Processor Datasheet For Intel® 965 Express Chipset Family September 2007 Revision 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

Contextual Info: CY7C1268KV18/CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:

TEA1507P

Abstract: TOP225Y MC44603P smd DAL TDA4605-3 stm cl 140 UC3842B 75155N 12v 60w smps MAX713CPE
Contextual Info: eratum.qxd 26/2/04 2:49 pm Page 1 Semiconductors - Power Supply & Control Switching Regulators Fixed Negative & Positive Type Manuf Package IOUT SW VOUT VIN (A)Max (V)Typ (V)Min-Max S/down SMT Features LT1300CN8 LT DIP8 0•62 3·3/5 1·8-8 N LM2597HVN-3·3