324 NAND GATE Search Results

mc14569

Abstract: mc14094b MC14024B MC14555B
Contextual Info: CMOS Selection Guide by Function Device NAND Gates MC14011B MC14011UB MC14093B MC14023B Function Page Quad 2−Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Quad 2−Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

324 quad nand gate

Abstract: dtl logic gates TSC321 324 Nand Gate 324 DIODE 5 input nand gate dtl CI 321 1N914 322 c r A0324
Contextual Info: Z J E T U 580 Pleasant Street Watertown, ma 0 217 2 I b E t - a / E T S C 3 2 1 / 3 2 2 / 3 2 3 /3 2 4 - r r / N A N D G a t e s • Quad 2 -In p u t Active Puliup ^ Quaj 5 . | n pUt (Active Pullup) • Quad 2 -In p u t (Open C ollector) • Quad 2 -In p u t (Passive Pullup)

A1742

Abstract: nec gate drive panel lcd nec gate drive panel THOMSON lcd 40 pin diagram lvds LCD panel timing control PD66208 nec b 708 nec LQFP-208
Contextual Info: New generation Gate Array with large scale embedded SRAM CMOS-12M CMOS-12M is NEC Electronics’ new generation Gate Array with embedded high-density SRAMs and analog PLLs. This product offers low price, quick design turnaroundtime and quick manufacturing turnaroundtime.

225VVCC

Abstract: H12G dm74as30n dm74as30
Contextual Info: ZW\ National OH Semiconductor DM74AS30 8 Input NAND Gate • Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Functionally and pin for pin compatible with Schottky, low power Schottky, and advanced low power Schottky TTL counterpart ■ Improved AC performance over Schottky, low power

Contextual Info: CT| National Jüâ Semiconductor DM54S30/DM74S30 8-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Connection Diagram Dual-ln-Line Package Vcc NC |l4 H 113 G NC NC |l0 11 12 Y • 19 >>I— 1 A

Contextual Info: oes ^ N a tio n a l j ü Semiconductor DM54S30/DM74S30 8-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Connection Diagram Dual-ln-Une Package V Cc NC H I« I. G NC ii 12 NC | io Y |a — i

PLC ELEVATOR CONTROL

Abstract: ELEVATOR LOGIC CONTROL PLC ELEVATOR CONTROL PLC MPC5125 what is PLC in fire alarm system e300z4 MPC5125YVN400 HDMI to ethernet chip hmi fire alarm HDMI to ethernet
Contextual Info: TOWER SYSTEM 32-bit Microprocessors MPC5125 For high-resolution display applications Overview MPC5125 Block Diagram The MPC5125 is a cost and power consumption optimized, industrial networking and human-machine interface HMI solution. Chip ID 256-bit OTP

XC5000

Abstract: decoder 7448 XC4005E/XL XC4003E 2C10 XC3000 CLB XC5000 architecture XC3000 XC4000 XC4006E
Contextual Info: APPLICATION BRIEF APPLICATION BRIEF An Alternative Capacity Metric for LUT-Based FPGAs  XBRF 011 Feb. 1, 1997 Version 1.0 Application Brief Summary tistics supplied by different FPGA vendors can be misleading. (The methodology used by Xilinx to generate gate

74as30

Contextual Info: NATIONAL SENICOND NATIONAL DE| b S G H E S SEMICONDUCTOR 61C 51618 National Semiconductor DOSlblfl □ 7 - H ir tç DM54AS30/DM74AS30 8 Input NAND Gate General Description Absolute Maximum Ratings Note d This device c o n ta in s a single gate w hich pe rform s the

AND Gate

Abstract: MC74VHC1G135 TTL 3 input or gate dual schmitt-trigger inverters NL27WZ07 MC74VHC1G09 MC74VHC1G00 MC74HC1G00 MC74HC1G14
Contextual Info: Selection Guide Buffers/Inverters Function Device Page Single Inverter MC74VHC1G04 60 Single Inverting Buffer/CMOS Logic Level Shifter MC74VHC1GT04 64 Single Unbuffered Inverter MC74VHC1GU04 68 Single Inverter with Open Drain Output MC74VHC1G05 76 Single Noninverting Buffer with Open Drain Output

XC4005E/XL

Abstract: decoder 7448 7448 decoder XC5000 datasheet 7448 2C10 2C26 decoder 7448 input 4 XILINX/XC4020E XC3000
Contextual Info: APPLICATION BRIEF APPLICATION BRIEF An Alternative Capacity Metric for LUT-Based FPGAs  XBRF 011 Feb. 1, 1997 Version 1.0 Application Brief Summary tistics supplied by different FPGA vendors can be misleading. (The methodology used by Xilinx to generate gate

full adder circuit using nor gates

Abstract: full adder circuit using xor and nand gates XC4005E/XL XC5000 figure of full adder circuit using nor gates circuit diagram of full adder circuit using nor XC4025E XC4000 XC4003E XC4006E
Contextual Info: APPLICATION NOTE Gate Count Capacity Metrics for FPGAs  XAPP 059 Feb. 1, 1997 Version 1.1 Application Note Summary Three metrics are defined to describe FPGA device capacity: Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. The methodology used to determine these values is described.

full adder circuit using xor and nand gates

Abstract: X4956 XC5000 sla9000 full adder circuit using nor gates Product Selection Guide xilinx XC4003E XC4005E XC4006E XC4008E
Contextual Info: APPLICATION NOTE Gate Count Capacity Metrics for FPGAs  XAPP 059 August 1, 1996 Version 1.0 Application Note Summary Three metrics are defined to describe FPGA device capacity: Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. The methodology used to determine these values is described.

AT91CAP7

Abstract: AT91CAP9S250A atmel 324 ARM926EJ-S AT91CAP9S500A
Contextual Info: CAP Ï CAP Customizable Microcontroller Platform Atmel’s CAP is a microcontroller-based system-on-chip platform with fast local memory, a wide range of industry-standard peripherals and interfaces, and a Metal Programmable MP Block that allows the designer to add custom logic. By combining

MC100EP809

Abstract: MC100EP210S MC10EP31 MC100EP35 MC10EP01 MC100EP31 MC10EPT20
Contextual Info: Numeric Data Sheet Listing Chapter 1: ECLinPS Plus Data Sheets Device Function Page MC10EP01, MC100EP01 . . . . . . 3.3V / 5V ECL 4−Input OR/NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 MC10EP05, MC100EP05 . . . . . . 3.3V / 5V ECL 2−Input Differential AND/NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Contextual Info: r z 7 SCS-THOMSON M54HC03 M74HC03 È QUAD 2-INPUT OPEN DRAIN NAND GATE HIGH SPEED tpz = 5 ns TYP. AT Vcc = 5 V LOW POWER DISSIPATION Icc = 1 nA (MAX.) AT Ta = 25 “C HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.) OUTPUT DRIVE CAPABILITY 1 0 LSTTLLOADS

NTE4097B

Contextual Info: INTEGRATED CIRCUITS - CMOS COMPLEMENTARY METAL OXIDE SILICON NTE4081B 14-Lead DIP, See Diag. 247 Quad 2-Input AND Gate NTE4082B Dual 4-Input AND Gate 14-Lead DIP, See Diag. 247 NTE4085B 14-Lead DIP, See Diag. 247 Dual 2-W ide, 2-Input AND/OR Invert Gate

transistor f422

Abstract: transistor f423 transistor f422 equivalent F422 F421 F423 L442 F924 uPD65 F324
Contextual Info: DATA SHEET CMOS-8L 3 Volt, 0.5-Micron CMOS Gate Array Description: Features: NEC’s CMOS-8L is an optimized true 3-Volt technology, targeted for applications requiring extensive integration, low power and high speed. The CMOS-8L ASICs are ideal for use in applications like

siemens master drive circuit diagram

Abstract: SR flip flop IC toshiba tc110g TC110G jk flip flop to d flip flop conversion SC11C1 JK flip flop IC siemens Nand gate scxc1 SR flip flop IC pin diagram
Contextual Info: SIEM EN S ASIC Product Description SCxC1 Family CMOS Gate Arrays FEATURES • Alternate source of Toshiba TC110G family ■ Densities up to 129,000 raw gates ■ Channelless “ sea of gates” architecture ■ 1.5 firn drawn CMOS technology, scalable to 1.0 /¿m

NTE4081B

Abstract: NTE4093B NTE4097B NTE4082B NTE4094B NTE4098B 14-LEAD NTE4099B NTE4096B NTE 4 E1
Contextual Info: INTEGRATED CIRCUITS - CMOS COMPLEMENTARY METAL OXIDE SILICON NTE4081B 14-Lead DIP, See Diag. 247 Quad 2-Input AND Gate NTE4082B Dual 4-Input AND Gate 14-Lead DIP, See Diag. 247 NTE4085B 14-Lead DIP, See Diag. 247 Dual 2-W ide, 2-Input AND/OR Invert Gate

ATMEL 340

Abstract: atmel atl atmel cpga ATL60 ATLS60 mux8n CERAMIC PIN GRID ARRAY 144 pins ambit inverter circuit AMBIT inverter ATMEL 218
Contextual Info: Features • 0.6 µm Drawn Gate Length 0.5 µm Leff Sea-of-Gates Architecture with Triple-level Metal • 5.0V, 3.3V and 2.0V Operation including Mixed Voltages • On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and • • •

74AC04N

Abstract: 74AC153N 74AC08N 74ac74n 74ac14 philips 74AC138N 74AC00N 74AC151N 74ac86N 74AC240N
Contextual Info: Standard Logic Thousands of new ICs are in the pipeline for addition and not shown below. Call us to see if you can save 10-20%. Package TI Jameco Fairchild On Semi ST Micro Philips Toshiba AC T DIP DIP SOIC SOIC SN74AC(T)XXXN CD74AC(T)XXXE SN74AC(T)XXXD/DW

66207

Abstract: nec 151 nec asic product letter
Contextual Info: 150 µm Structured ASICs CMOS-12M Structured Array Product Letter Description CMOS-12M is NEC Electronics’ new structured array technology with embedded highdensity SRAMs and analog PLLs. The technology enables the integration of large size SRAM modules in structured array and is capable of supporting up to 2.6 Mb of embedded

74ls08n

Abstract: 74ls04n 74LS14N 74LS07N 74LS05N 74LS11N 74ls06n 74LS02N IC 74LS14 74ls04 hex inverter
Contextual Info: Standard Logic Call us to see if you can save 10-20%. 74F Series Continued – General purpose family of high speed advanced bipolar logic DIP SOIC Save Up To 20% When Purchasing Texas Instruments Products. Save Up To 30%! Jameco Value Offering Jameco now offers two ways to save! Our selection of Texas Instruments products will save you