3GPP2 Search Results

Contextual Info: Pb MSL1 Pb-free * Pb Free Part Customer Name Standard Specification System 3GPP2:BC10 and 3GPP:B5+B18 Rx 50/100ohm Date Part Number F5KY877M0B4NH Version 1.0 a Jan. 30, 2013 Final Table 1.Electrical specifications Passband : 860 ~ 894 MHz Item Condition

xilinx TURBO decoder

Abstract: DS275 Turbo Code LogiCORE IP License Terms XC2V500 XC2VP20 Turbo decoder Xilinx RSC11
Contextual Info: 3GPP2 Turbo Decoder v1.0 DS275 April 28, 2005 Product Specification Features Applications • Drop-in module for Spartan -3, Spartan-3E, This version of the TCC Turbo Convolution Code decoder is designed to meet the 3GPP2 mobile communication system specification [1].

Contextual Info: Pb MSL1 Pb-free * Pb Free Part Customer Name Standard specification System 3GPP2 BC0+BC10 Tx 50/50ohm DATE Aug. 10 , 2011 Part Number F5KA833M0D4DU Version 5.0 f Final Table 1.Electrical specifications Item Condition Insertion Loss Ripple Specification Unit

Contextual Info: Data Sheet of SAW Components Note : Murata SAW Component is applicable for Cellular /Cordless phone Terminal relevant market only. Please also read caution at the end of this document. SAW DPX FOR UMTS E850 3GPP:B26/5/6/18/19/GSM850 3GPP2:BC10SC2&3/BC0 Murata part number :SAYFH831MCA0F0A

Crest factor reduction

Abstract: baseband processor OFDM LTE OFDM FPGA 4G OFDM QPSK simulation lte if filter ofdm amplifier ofdm datasheet PAR ofdm LTE OFDM MIMO 4G LTE PA
Contextual Info: White Paper Crest Factor Reduction for OFDM-Based Wireless Systems Introduction Orthogonal frequency division multiplexing OFDM is regarded widely as the key underlying air interface technology for wireless systems such as WiMAX, 3GPP long-term evolution (LTE), and 3GPP2 ultra-mobile

vhdl codes for Return to Zero encoder in fpga

Abstract: rsc Encoder Turbo Decoder turbo encoder design using xilinx DS604 vhdl code for CDMA turbo-code convolution encoder with interleaver turbo codes using vhdl MULT18X18S
Contextual Info: 3GPP2 Turbo Encoder v2.0 DS604 April 2, 2007 Product Specification Features LogiCORE Facts • Drop-in module for Virtex -II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, Spartan-3E, Spartan-3A/3AN/3A DSP FPGAs Core Specifics • Implements the 3GPP2/CDMA-2000 Turbo Encoder

Convolutional Encoder

Abstract: Convolutional CORE i3 block diagram Convolutional Puncturing Pattern LFEC20E-5F672C GP113
Contextual Info: Block Convolutional Encoder September 2004 IP Data Sheet Features General Description • Compatible with the Following Standards: IEEE 802.16, IEEE 802.16a, IEEE 802.11a, 3GPP, 3GPP2 and DVB-S Lattice’s Block Convolutional Encoder IP core is a parameterizable core for convolutional encoding of a

Contextual Info: Pb MSL1 Pb-free * Pb Free Part Customer Name Standard specification System 3GPP2 BC0+BC10 Rx 50/100ohm DATE Part Number F5KY878M0B4ND Version 1.0 a June 30, 2010 Table 1.Electrical specifications Item Condition Insertion Loss Ripple Specification Unit Min.

Contextual Info: TMS320TCI100 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS218H − MAY 2003 − REVISED JUNE 2006 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors DSPs − 1.67-, 1.39-ns Instruction Cycle Time − 600-, 720-MHz Clock Rate − Eight 32-Bit Instructions/Cycle

D6PE2G140P3AW

Abstract: FAR-D5PE-881M50-P3EY F6QG2G140P2KA JISC60068-2-21 G6QH2G140N2LA D6HH1G960BH97 F6KB2G595B4HS D5NG782M0M15Z F6KA2G436A4VE D5PE942M5P3GT
Contextual Info: Notice for TAIYO YUDEN products Please read this notice before using the TAIYO YUDEN products. REMINDERS • Product information in this catalog is as of October 2011. All of the contents specified herein are subject to change without notice due to technical improvements, etc. Therefore, please check for the latest information carefully before practical application or usage of the Products.

Contextual Info: TMS320C6414T, TMS320C6415T, TMS320C6416T FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS SPRS226F − NOVEMBER 2003 − REVISED MARCH 2005 D Highest-Performance Fixed-Point DSPs D D D D D − 1.67-/1.39-/1.17-/1-ns Instruction Cycle − 600-/720-/850-MHz, 1-GHz Clock Rate

Contextual Info: SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors DSPs − 2-, 1.67-, 1.39-ns Instruction Cycle Time − 600-MHz Clock Rate

Contextual Info: SM320C6414-EP, SM320C6415-EP, SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008 1 Introduction 1.1 Features • • • • • • • Highest-Performance Fixed-Point Digital Signal Processors DSPs

BR17

Contextual Info: TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com TMS320C6474 Multicore Digital Signal Processor 1 Features 12 • Key Features – High-Performance Multicore DSP C6474 – Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns

Contextual Info: SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date.

Contextual Info: TMS320C6414, TMS320C6415, TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146N − FEBRUARY 2001 − REVISED MAY 2005 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors DSPs − 2-, 1.67-, 1.39-ns Instruction Cycle Time − 500-, 600-, 720-MHz Clock Rate

GC1115

Contextual Info: GC1115 www.ti.com SLWS144 – FEBRUARY 2005 Crest Factor Reduction Processor FEATURES APPLICATIONS • • • • • • • • • • • • • • Significantly Reduces Signal Peaks to ≥ 6 dB PAR One 20-MHz or 2 Independent 10-MHz Channels Programmable Output PAR Down to 6 dB

MAR105

Contextual Info: SM320C6414-EP, SM320C6415-EP, SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008 1 Introduction 1.1 Features • • • • • • • Highest-Performance Fixed-Point Digital Signal Processors DSPs

Contextual Info: SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors DSPs − 2-, 1.67-, 1.39-ns Instruction Cycle Time − 600-MHz Clock Rate

Contextual Info: SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors DSPs − 2-, 1.67-, 1.39-ns Instruction Cycle Time − 600-MHz Clock Rate

7813 Texas Instruments Transistor

Abstract: TMS320C6000 TMS320C6474 C6000 C6474 C64X DDR2-667 SPRS552H BR17
Contextual Info: TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com TMS320C6474 Multicore Digital Signal Processor 1 Features 12 • Key Features – High-Performance Multicore DSP C6474 – Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns

Contextual Info: TMS320C6455 Fixed-Point Digital Signal Processor www.ti.com SPRS276F – MAY 2005 – REVISED MARCH 2007 1 TMS320C6455 Fixed-Point Digital Signal Processor 1.1 Features • • • • • • • High-Performance Fixed-Point DSP C6455 – 1.39-, 1.17 and 1-ns Instruction Cycle Time

MAR138

Contextual Info: TMS320C6414T, TMS320C6415T, TMS320C6416T FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 D Highest-Performance Fixed-Point DSPs D D D D D − 1.67-/1.39-/1.17-/1-ns Instruction Cycle − 600-/720-/850-MHz, 1-GHz Clock Rate

mar105

Abstract: EMIFA OMAP
Contextual Info: SM320C6414-EP, SM320C6415-EP, SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008 1 Introduction 1.1 Features • • • • • • • Highest-Performance Fixed-Point Digital Signal Processors DSPs