40 PIN LVDS Search Results

Contextual Info: 19-2829; Rev 1; 7/03 Anything-to-LVDS Dual 2 x 2 Crosspoint Switches Ordering Information TEMP RANGE PIN-PACKAGE MAX9390EHJ PART -40°C to +85°C 32 TQFP MAX9390ETJ* -40°C to +85°C 32 Thin QFN MAX9391EHJ -40°C to +85°C 32 TQFP MAX9391ETJ* -40°C to +85°C

33 pin LCD connector

Abstract: rj45 socket 8 pin to usb port 4 pin 40 pin LCD cable SBC-657 VT8606 LVDS 40 pin lcd AEC-204S1-01 VIA VT8606 vt82c686b 36 dstn VIA VT8606
Contextual Info: SBC-657 1 VIA C3 Low Power Processor LVDS LCD pin header CFD slot back USB pin header Full-size SBC TTL LCD pin header FDD connector 40-pin IDE connector 2 Features Onboard VIA C3™ Low Power Processor Printer port pin header 36/18-bit Dual Channels LVDS/TTL TFT/DSTN LCD

EIA-644

Abstract: AD5371
Contextual Info: 40-Channel, 14-Bit Serial Input, Voltage-Output DAC AD5371 Preliminary Technical Data Power-on reset Digital reset RESET Clear function to user-defined SIGGND (CLR pin) Simultaneous update of DAC outputs (LDAC pin) FEATURES 40-channel DAC in 80 Lead LQFP and 100 Ball CSPBGA

Contextual Info: 40-Channel, 14-Bit Serial Input, Voltage-Output DAC AD5371 Preliminary Technical Data Power-on reset Digital reset RESET Clear function to user-defined SIGGND (CLR pin) Simultaneous update of DAC outputs (LDAC pin) FEATURES 40-channel DAC in 80 Lead LQFP and 100 Ball CSPBGA

SPI LVDS

Abstract: AD5371 EIA-644 2T324
Contextual Info: 40-Channel, 14-Bit Serial Input, Voltage-Output DAC AD5371 Preliminary Technical Data Power-on reset Digital reset RESET Clear function to user-defined SIGGND (CLR pin) Simultaneous update of DAC outputs (LDAC pin) FEATURES 40-channel DAC in 80 Lead LQFP and 100 Ball CSPBGA

Contextual Info: 40-Channel, 14-Bit Serial Input, Voltage-Output DAC AD5371 Preliminary Technical Data Power-on reset Digital reset RESET Clear function to user-defined SIGGND (CLR pin) Simultaneous update of DAC outputs (LDAC pin) FEATURES 40-channel DAC in 80 Lead LQFP and 100 Ball CSPBGA

higig2

Abstract: SSTL-15 EP4SGX360F CEI-6G-SR SSTL15 EP4SE230 EP4SE360 EP4SGX290 EP4SGX530N EP4SGX360K
Contextual Info: Stratix IV FPGA family package and I/O selector guide 560 560 560 560 560 736 736 560 2 736 Stratix III FPGAs Balanced logic, memory, DSP 480 2 480 2 1,152-pin 35 x 35 mm 736 736 1,517-pin 40 x 40 mm 864 864 1,760-pin 43 x 43 mm 736 2 736 2 960 960 960 1,104

I-64.1

Abstract: TRV709 300-Pin trv5019 trv7058 OpNext 10gbase sr 300-pin opnext trv7068 GR-253 TRV5029EZ
Contextual Info: Products Products 300-pin Transponder SerDes Transceiver Modules Opnext offers 300-pin Transponders for the following Data Rates / Applications ● ● ● 40 Gbit/s 10 Gbit/s IR/LR 10 Gbit/s SR 40 Gbit/s 40G Features ● ● ● ● ● ● ● Laser Class 1

SLLS526

Abstract: SN65LVDS1021DB SN65LVDS1212 SN65LVDS1212DB SN65LVDS1021
Contextual Info: SN65LVDS1021/SN65LVDS1212 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526 – FEBRUARY 2002 D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212 Chipset Serializer/Deserializer Power

SLLS526A

Contextual Info: SN65LV1021/SN65LV1212 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526A – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

serializer guide

Abstract: SLLS526E 8208 ns
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526E – FEBRUARY 2002 – REVISED SEPTEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM

40mhz receiver circuit

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

SLLS526C

Contextual Info: SN65LV1021/SN65LV1212† 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526C – FEBRUARY 2002 – REVISED MAY 2002 D D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

Contextual Info: 19-2913; Rev 0; 8/03 Anything-to-LVDS Dual 2 x 2 Crosspoint Switches Also see the MAX9390/MAX9391 for the crossflow version. Ordering Information TEMP RANGE PIN-PACKAGE MAX9392EHJ PART -40°C to +85°C 32 TQFP MAX9392ETJ* -40°C to +85°C 32 Thin QFN MAX9393EHJ

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

10-bit-serdes

Abstract: MO-150 SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

MO-150

Abstract: SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

MO-150

Abstract: SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212 SLLS526B
Contextual Info: SN65LV1021/SN65LV1212† 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526B – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

SLLS526D

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

LZ 02

Abstract: MO-150 SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

Contextual Info: M5RJ Series 9x14 mm, 3.3 Volt, LVPECL/LVDS, Clock Oscillator • • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications Pin Connections Z, E, and R Output Types Pin Connections

Contextual Info: M5RJ Series 9x14 mm, 3.3 Volt, LVPECL/LVDS, Clock Oscillator • • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications Pin Connections Z, E, and R Output Types Pin Connections

Contextual Info: M5RJ Series 9x14 mm, 3.3 Volt, LVPECL/LVDS, Clock Oscillator • • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications Pin Connections Z, E, and R Output Types Pin Connections