40 PIN LVDS TO 20 PIN Search Results
40 PIN LVDS TO 20 PIN Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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MG80C196KB |
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80C196KB - Microcontroller, 16-bit, MCS-96, 68-pin Pin Grid Array (PGA) |
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PAL16L8B-4MJ/BV |
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PAL16L8B - 20 Pin TTL Programmable Array Logic |
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PAL16L8-7PCS |
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PAL16L8 - 20-Pin TTL Programmable Array Logic |
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54F191/Q2A |
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54F191 - Up/Down Binary Counter with Preset and Ripple Clock. Dual marked as DLA PIN 5962-90582012A. |
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TDC1044AR4C |
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TDC1044A - ADC, Proprietary Method, 4-Bit, 1 Func, 1 Channel, Parallel, 4 Bits Access, Bipolar, PQCC20 |
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40 PIN LVDS TO 20 PIN Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: M5RJ Series 9x14 mm, 3.3 Volt, LVPECL/LVDS, Clock Oscillator • • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications Pin Connections Z, E, and R Output Types Pin Connections |
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Contextual Info: M5RJ Series 9x14 mm, 3.3 Volt, LVPECL/LVDS, Clock Oscillator • • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications Pin Connections Z, E, and R Output Types Pin Connections |
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mtronContextual Info: M5RJ Series This product is not recommended for new designs 9x14 mm, 3.3 Volt, LVPECL/LVDS, Clock Oscillator • • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications Pin Connections |
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Contextual Info: UVCJ Series 5x7 mm, 3.3 Volt, LVPECL/LVDS, Clock Oscillators • • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications DENOTES PIN 1 Pad Connections Pad Function 1 Enable/Disable for “B” or “S” Output Type |
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Contextual Info: UVCJ Series 5x7 mm, 3.3 Volt, LVPECL/LVDS, Clock Oscillators • • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications DENOTES PIN 1 MtronPTI reserves the right to make changes to the product s and service(s) described herein without notice. No liability is assumed as a result of their use or application. |
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lvds buffer
Abstract: DS15MB200 DS15MB200TSQ DS15MB200TSQX AN-1187 AN-1194
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DS15MB200 DS15MB200 CSP-9-111S2) CSP-9-111S2. lvds buffer DS15MB200TSQ DS15MB200TSQX AN-1187 AN-1194 | |
Contextual Info: DS15MB200 Dual 1.5 Gbps 1:2/2:1 LVDS Mux/Buffer with Pre-emphasis General Description Features The DS15MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from |
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DS15MB200 | |
lvds buffer
Abstract: DS15MB200TSQ DS15MB200TSQX AN-1187 AN-1194 DS15MB200
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DS15MB200 DS15MB200 CSP-9-111S2) CSP-9-111S2. lvds buffer DS15MB200TSQ DS15MB200TSQX AN-1187 AN-1194 | |
DS15BR400
Abstract: DS15BR400EVK AN-1194 DS15BR401 TQFP-48
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DS15BR400/DS15BR401 DS15BR400/DS15BR401 DS15BR400 DS15BR401 DS15BR400EVK AN-1194 TQFP-48 | |
DS15BR400
Abstract: AN1194 DS15BR400EVK DS15BR401 TQFP-48
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DS15BR400/DS15BR401 DS15BR400/DS15BR401 DS15BR400 DS15BR401 AN1194 DS15BR400EVK TQFP-48 | |
DS2013
Abstract: lvds 44 pin AN-1187 AN1194 AN-1313 SCAN15MB200 SCAN15MB200TSQ SCAN15MB200TSQX
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SCAN15MB200 SCAN15MB200 CSP-9-111S2) CSP-9-111S2. DS2013 lvds 44 pin AN-1187 AN1194 AN-1313 SCAN15MB200TSQ SCAN15MB200TSQX | |
Contextual Info: SCAN15MB200 Dual 1.5 Gbps 1:2/2:1 LVDS Mux/Buffer with Pre-emphasis and IEEE 1149.6 General Description Features The SCAN15MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from |
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SCAN15MB200 | |
Contextual Info: SCAN15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 General Description Features The SCAN15MB200 is a dual-port 2 to 1 multiplexer and 1 to 2 repeater/buffer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from |
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SCAN15MB200 | |
Contextual Info: ZL40226 Precision 2:8 LVDS Fanout Buffer with Simple Input Reference Switching Data Sheet February 2013 Features Ordering Information ZL40226LDG1 ZL40226LDF1 32 Pin QFN Trays 32 Pin QFN Tape and Reel Matte Tin Package size: 5 x 5 mm -40oC to +85oC Inputs/Outputs |
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ZL40226 ZL40226LDG1 ZL40226LDF1 -40oC | |
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maxim 1909
Abstract: DS90LV048A MAX9121 MAX9121ESE MAX9121EUE MAX9122 MAX9123
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MAX9122) DS90LV048A 500Mbps 300ps TIA/EIA-644 MAX9121EUE MAX9121ESE MAX9122EUE MAX9122ESE MAX9121/MAX9122 maxim 1909 DS90LV048A MAX9121 MAX9121ESE MAX9121EUE MAX9122 MAX9123 | |
330nF capacitorContextual Info: 19-1498; Rev 1; 12/99 KIT ATION EVALU E L B A AVAIL +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs Features ♦ Single +3.3V Supply The MAX3890 is available in the extended temperature range -40°C to +85°C in a 64-pin TQFP exposed-pad |
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MAX3890 16-bitwide, 155Mbps 52MHz, 76MHz, 84MHz, 88MHz 10x10x1mm 21-0084C 330nF capacitor | |
Contextual Info: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four The MAX9377/MAX9378 accept any differential input signal within the supply rails and with minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling |
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MAX9377/MAX9378 100mV. MAX9377 MAX9378 EIA/TIA-644 MAX9377/MAX9378 | |
MAX9377
Abstract: MAX9377EUA MAX9378 MAX9378EUA
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421ps MAX9377) 100mV MAX9377EUA MAX9378EUA* MAX9377/MAX9378 MAX9377 MAX9377EUA MAX9378 MAX9378EUA | |
MAX9378
Abstract: MAX9377 MAX9377EUA MAX9378EUA
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421ps MAX9377) 100mV MAX9377EUA MAX9378EUA MAX9377/MAX9378 MAX9378 MAX9377 MAX9377EUA MAX9378EUA | |
Contextual Info: ZL40226 Precision 2:8 LVDS Fanout Buffer with Simple Input Reference Switching Data Sheet April 2014 Features Ordering Information ZL40226LDG1 ZL40226LDF1 32 Pin QFN Trays 32 Pin QFN Tape and Reel Matte Tin Package size: 5 x 5 mm -40oC to +85oC Inputs/Outputs |
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ZL40226 ZL40226LDG1 ZL40226LDF1 -40oC | |
Contextual Info: ZL40220 Precision 2:6 LVDS Fanout Buffer with Glitch-free Input Reference Switching Data Sheet April 2014 Features Ordering Information ZL40220LDG1 32 Pin QFN Trays ZL40220LDF1 32 Pin QFN Tape and Reel Inputs/Outputs • Accepts two differential or single-ended inputs |
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ZL40220 ZL40220LDG1 ZL40220LDF1 -40oC | |
Contextual Info: ZL40215 Precision 1:4 LVDS Fanout Buffer with On-Chip Input Termination Data Sheet April 2014 Ordering Information Features ZL40215LDG1 ZL40215LDF1 Inputs/Outputs • Accepts differential or single-ended input • LVPECL, LVDS, CML, HCSL LVCMOS 16 Pin QFN |
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ZL40215 ZL40215LDG1 ZL40215LDF1 | |
Contextual Info: April 2005 DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS90LV004 is a four channel 1.5 Gbps LVDS buffer/ repeater. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, |
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DS90LV004 | |
ZL40215
Abstract: zl40215LDF1 ZLAN-403
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ZL40215 ZL40215LDG1 ZL40215LDF1 -40oC ZLAN-403 |