4515B Search Results

Contextual Info: COS/MOS INTEGRATED CIRCUITS _ n 4 ^ /+ » ‘¡ ¡ S Ä 4-BIT LATCH/4-TO-16 LINE DECODER: HCC/HCF 4514B OUTPUT "H IG H" ON SELECT HCC/HCF 4515B OUTPUT "LOW" ON SELECT • • • • • • Q UIESCENT C U R R E N T SPECIFIED TO 2 0 V FOR HCC D EVICE STRO BED INPUT LATC H

Contextual Info: b llò / m u ò S G S “ T H 0 ,V ,S 0 N D 7C IM TFRRATFil L. - a . « CIRCUITS 7929225 ß I ? c >2 ^ 2 3 7 ^ I o o i^ a ? a | ^ HCG/HCF 4515B-A — ✓ j . i S G S S EM IC O N D U C T O R C O R P 4-BIT L A TCH/4-T0-16 LIN E DECODER: HCC/HCF 4514B OUTPUT "HIGH" ON S ELE C T

Contextual Info: R&E 4514B 4515B INTERNATIONAL, INC. CMOS 4-T0-16 LINE DECODERS WITH LATCH FEATURES ♦ ♦ ♦ Strobed Input Latch Inhibit Control Selected Output Active High 4514B or Active Low (4515B) DESCRIPTION 1 TRUTH TABLE (Strobe - 1) Data Inputs Selected Output

4514B

Abstract: D 4515 4000B 4515B 4T016 AICB
Contextual Info: 4514B 4515B INTERNATIONAL, INC. CMOS 4-T0-16 LINE DECODERS WITH LATCH FEATURES ♦ ♦ ♦ Strobed Input Latch Inhibit Control Selected Output Active High 4514B or Active Low (4515B) DESCRIPTION CONNECTION DIAGRAM (all packages) D ata Inputs Vqd The 4514B and 4515B are two out*

Contextual Info: R&E 4514B 4515B INTERNATIONAL, INC. CMOS 4-T0-16 LINE DECODERS WITH LATCH FEATURES ♦ ♦ 4 Strobed Input Latch Inhibit Control Salactad O utput Activa High 4514B or Activa Low (4515B) DESCRIPTION The 4514B and 4515B are two out­ put options o f a 4-to -16 Line Decoder w ith

ITS 7166

Abstract: 7166 cmos D 4515 4000B 4515B
Contextual Info: 4515B l-O F-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH D E S C R IP T IO N — T h e 4 5 1 5 B is a 1 -o f-1 6 D e c o d e r/D e m u ltip le x e r w it h fo u r b in a ry w e ig h te d A d d re ss In p u ts A 0 - A 3 , a L a tc h E n a b le I n p u t (E L ), an a c tiv e L O W E n a b le I n p u t (E ) a nd s ix te e n m u tu a lly

7166 cmos

Contextual Info: GOLDSTAR TECHNOLOGY INC-. D4E D | 4GEÖ7S7 00G17t,fl ñ | 4 0 2 8 7 5 7 G O L D S TA R TECHNOLOGY 04E INC. 01768 D T -4 7 -//-S / 4515B l-OF-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH DESCRIPTION - The 4515B is a 1-of-16 Decoder/Demultiptexer with four binary weighted Address

kcc CL-60

Abstract: transistor hh 004 circuits diagram transistor d 4515
Contextual Info: b llò / m u ò S G S “ T H 0 ,V ,S 0 N D 7C ß IM TFRRATFil L. - a . « I ? c >2 ^ 2 3 7 ^ C IR C U IT S I ^ o o i^ a ? | HCG/HCF 4515B-A — 7929225 a ✓ j . i S G S SEMICONDUCTOR CORP 4 -B IT LA T C H /4 -T 0 - 1 6 L IN E DEC O D ER: H C C /H C F 4514B O U T P U T " H IG H " ON SELECT

i.c. cmos 4514b

Abstract: 4514B 45148 D 4515 4000B 4515B
Contextual Info: 4514B 4515 B INTERNATIONAL, INC CMOS 4-T0-16 LINE DECODERS WITH LATCH FEA TU R ES ♦ Strobed Input Latch ♦ Inhibit Control ♦ Selected Output Active High 4514B or Active Low (4S15B) D ESC RIPTIO N The 45146 and 4515B are two out­ put options of a 4-to-16 Lin« Decoder with

N23A

Abstract: circuits of cd4514 mc14514 CD4514BC CD4514BCN CD4514BCWM CD4515BC M24B MC14515 MS-013
Contextual Info: Revised January 1999 EMICONDUCTGRTM CD4514BC« 4515BC 4-Bit Latched/4-to-16 Line Decoders General Description Features T he C D 4514BC and C D 4515BC are 4-to-16 line decoders w ith latched inputs im plem ented with com plem entary MOS CMOS circuits constructed with N- and P-channel

Contextual Info: 4515B l-O F-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH D E S C R IP T IO N — The 4 5 1 5B is a 1-of-16 D ecoder/D em ultiplexer w ith four binary weignted Address C O N N E C T IO N D IA G R A M D IP TO P VIEW Inputs (A 0 - A 3 ), a Latch Enable Input (E L), an active L O W Enable Input (E) and sixteen m utually

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCI 4514B MCI 4515B 4-Bit Transparent Latch/4-to-16 Line Decoder The MC14514B and 4515B are two output options of a 4 to 16 line decoder with latched inputs. The MC14514B output active high option presents a logical “1” at the selected output, whereas the 4515B (output

CD4514BC

Abstract: CD4514BCN CD4514BCWM CD4515BC M24B MC14514 MC14515 MS-013 N24A
Contextual Info: Revised Ja nuary 1999 S E M I C O N D U C T O R TM CD4514BC« 4515BC 4-Bit Latched/4-to-16 Line Decoders Features • W ide supply voltage range: The C D 4514BC output active high option presents a logi­ cal “ 1” at the selected output, w hereas the C D 4515BC pre­

C14516

Abstract: 14514B
Contextual Info: MOTOROLA SC -CLO fiïO Tñ DE J b3L.72SH □ Q 7 ‘i b cm 6 3 6 7 2 5 2 M O T O R O L A SC LOGIC 4 980 79694 — M t ~ ¿ 7 - / / - £ ;/ MC14514B MCI 4515B O T O R O L A CMOS MSI 4-BIT TRANSPARENT LATCH/4-TO-16 LINE DECODER T h e M C 14514B and M C 4515B are two output options of a 4 to

Contextual Info: 4515B MSI 1-OF-16 DECODER/DEMULTIPLEXER WITH INPUT LATCHES T he H E F 4515B is a 1-of-16 d e co de r/d e m u ltip lexe r, having fo u r b in a ry weighted address in p jjts A g to A 3 , a latch enable in p u t (E L ), and an active LOW enable in p u t (F). The 16 o u tp u ts (Oo to O 1 5 ) are

HEF4515B

Contextual Info: 4515B J 1 -0 F -1 6 D E C O D E R /D E M U L T IP L E X E R W IT H I MSI - IN P U T L A T C H E S The H E F 4515B is a 1-of-16 decoder/demultiplexer, having four binary weighted address inputs Ag to A 3 , a latch enable input (E L ), and an active LOW enable input (E). The 16 outputs (Oo to O 15 ) are

4515BP

Contextual Info: 4515B MSI 1-OF-16 DECODER/DEMULTIPLEXER WITH INPUT LATCHES ' The H E F 4515B is a 1-of-16 d e co d e r/d e m u ltip le xe r, having fo u r b in a ry w eighted address in p u ts A g to A 3 , a latch enable in p u t (E L ), and an active LOW enable in p u t (E). The 16 o u tp u ts (O o to O 1 5 ) are

TC74HC4515P

Contextual Info: TOSHIBA 14E 0 I IGTPEMä GQÌÒb03 S | LOGIC/MEMORY TC74HC4514P_ TC74HC4515P TC74HC4514P 4-T0-16 LINE DECODER/LATCH TC74HC4515P 4-T0-16 LINE DECODER/LATCH INV. The TC74HC4514 and TC74HC4515 a re h ig h speed CMOS 4-LINE TO 16-LINE DECODER WITH LATCHED INPUTS f a b r ic a te d w ith s i l i c o n g a te C MOS tec h n o lo g y . I t a c h ie v e s th e h ig h

40528

Abstract: astable Multivibrator 74 4557* cmos 4052B 4051B 4731B ci 4047B 4008B 4034b 40518 ic pin connection
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-CMOS C62 4104B © © © C63 4016B, 4066B © : Pin 1 vDDO V DDI = pin 16 VSS = Pin 8 C64 4052B 12 14 15 11 1 5 2 4 I II I I I I I 10 - V0aVls Y2a Y3aY0bY,bV2bY3b A0 9 • VDD " Pin 14 Zb T 13 Vgg = Pin 8 V EE = Pin 7

Contextual Info: M74HC4514 M74HC4515 SGS-THOMSON iy HC4514:4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH INV. HIGHSPEED tpD = 18 ns (TYP.) AT Vcc = 5 V LOW POWER DISSIPATION Icc = 4 nA (MAX.) AT Ta = 25 °C HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.)

Contextual Info: R&E 4555B 4556B INTERNATIONAL, INC. CMOS DUAL 2-T0-4 LINE DECODERS FEATURES ♦ Buffered Outputs ♦ Selected Output Active High 4555B or Active Low (45S6B) Expandable ♦ CONNECTION D IA G R A M (all packages) Vd d I 16 DESCRIPTION The 4555 B and 4556B are constructed

Contextual Info: 4518B 4520B INTERNATIONAL, INC. CMOS DUAL UP COUNTERS FEATURES 4 Two Independent 4-B it Counters 4 Internally Synchronous fo r High Speed Dual BCD 4518B and Dual Binary (4520B) Configurations 4 D irect Reset 4 Logic Edge-Clocked Design 4 Trigger from either Edge o f Clock Signal

D 4515

Abstract: 4514B P043A
Contextual Info: HCC/HCF4514B HCC/4515B 4-BIT LATCH/4-TO-16 LINE DECODER HCC/HCF4514B OUTPUT ”HIGH” ON SELECT HCC/4515B OUTPUT ”LOW” ON SELECT . . . . QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE STROBED INPUT LATCH INHIBIT CONTROL INPUT CURRENT OF 100nA AT 18V AND 25°C

HC772

Abstract: TC74HC4515A
Contextual Info: TC74HC4514AP_ TC74HC4515AP TC74HC4514AP 4 - T O - 1 6 LINE DECODER/LATCH T C 74H C 461SA P 4 - T O - 1 6 LIN E D ECODER/LATCH INV. The TC74HC4514A/TC74HC4515A are high speed CMOS 4 -L IN E TO 16-L IN E DECOD ER WITH LATCH ED IN PU T s fab ricated with silicon gate C2MOS technology.