4VFX12 Search Results

4VFX12-12

Contextual Info: Complies with the USB 2.0 specification USBHS-HUB USB Hi-Speed Embedded Hub Controller Core The USBHS-HUB core implements a hi-speed configurable USB Hub controller that can serve as an interface between a USB host and multiple USB peripheral devices, each

6SLX45-2

Abstract: 3s500e-5 4VFX12
Contextual Info: Complies with the USB 2.0 specification and its On-The-Go supplement USBHS-OTG-SD Supports one Low-Speed, FullSpeed, or High-Speed peripheral device in Host mode USB2.0 On-The-Go Controller Core Supports Full-Speed and HighSpeed data transfer in Peripheral mode

R8051XC

Abstract: usbfs-5 3S1600E
Contextual Info:  Support for Full and Low Speed operation according to the USB 2.0 specification  Generic system bus interface USBFS-DEV  Serial Interface Engine USB Full-Speed Device Controller Core  Support full speed devices  Extraction clock and data sig-

Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT-FI  Low gate count 2D Forward and Inverse Discrete Cosine Transform Core  Low latency (89 cycles)  Single clock cycle per sample operation on both directions

SDLC

Abstract: 3s250E IN SDLC PROTOCOL 80C152 intel 8051 application information xilinx spartan SDLC synchronous signals
Contextual Info: Based on Intel’s 80C152 Global Serial Channel Flexible addressing schemes SDLC Controller Core The SDLC controller is a synthesizable HDL core providing a high-speed synchronous serial communication interface. Operation of the controller is similar to that used in the Intel 8XC152 Global Serial

Virtex-4

Abstract: ds-kit-4vfx12lc virtex memec The Virtex-4 LC system board DS-KIT-4VFX12LC-EDK-EURO xilinx vhdl rs232 code DS-KIT-4VFX12LC-EDK DS-KIT-4VFX12 Virtex-4 prototype platform board virtex-4 lc
Contextual Info:  Virtex-4 FX LC Development Kit The perfect solution for FPGA and system designers who need a low cost, flexible prototype platform. The Memec Virtex-4 FX LC Development Kit is the ideal solution for investigating the embedded PowerPC and tri-mode Ethernet MAC included in

3S100E-5

Abstract: 8051 THROUGH I2C PROTOCOL ahb to i2c design implementation 89C51IC2 "programmable clock" i2c texas ahb to i2c testbench of a transmitter in verilog
Contextual Info: I2C-HS Master/Slave Bus Controller Core The I2C-HS core implements a serial interface that meets the Philips I2C Bus specification version 2.1. It is compliant with the PVCI Peripheral Virtual Component Interface standard which is an open standard for SoC On-Chip Bus.

dct verilog code

Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT  Low gate count  Single clock cycle per sample 2-D Forward Discrete Cosine Transform Core operation  Low latency (87 cycles) Design Quality The DCT core implements the 2D Forward Cosine Transform. Most of the image/video

dct verilog code

Abstract: IDCT xilinx
Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies IDCT  Low gate count  Single clock cycle per sample 2-D Inverse Discrete Cosine Transform Core operation  Low latency (86 cycles) Design Quality The IDCT core implements the 2D Inverse Cosine Transform. Most of the image/video

3S100E-5

Abstract: 80C552
Contextual Info: I2C Master/Slave Bus Controller Core The I2C core implements a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus. The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register i2csta reflects the status of I2C Bus Controller and the I2C

ML403

Abstract: ML403 system clock jtag option pin location 4vfx12ff668 ppc405 JTGC405TCK JTGC405TDI JTGC405TMS XAPP575 XAPP719 XC4VFX12
Contextual Info: Application Note: Virtex-4 FX Family R XAPP719 v1.1 March 13, 2006 Summary PowerPC Cache Configuration Using the USR_ACCESS_VIRTEX4 Register Author: Nick Camilleri and Peter Ryser The Virtex -4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register that