512K X 8 BIT SRAM Search Results

A81L801

Abstract: 69LD
Contextual Info: A81L801 Stacked Multi-chip Package MCP 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM Preliminary Document Title Stacked Multi-chip Package (MCP) 1M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM

68S16000

Abstract: AB-020
Contextual Info: 512K x 32 SRAM MODULE PUMA 68S16000/AB-020/025/35/45 Issue 5.0 : May 2001 • User Configurable as 8 / 16 / 32 bit wide output. • Operating Power : • Standby Power : CMOS • Single 5V±10% Power supply. 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM CS1

Contextual Info: LINVEX TECHNOLOGY, CORP. PRELIMINARY LX59CF4128 512K x 8 Bit FLASH and 128K x 8 Bit SRAM Low Voltage Combo Memory FEATURES GENERAL DESCRIPTION • • • The LX59CF4128 is a combination memory chip consist of 4M-bit FLASH Memory organized as 512K words by 8 bits and a 1-Meg-bit Static

AK68512D1C

Abstract: 850C 512K x 8 bit Low Power CMOS Static RAM 512K x 8 bit sram 32 pin
Contextual Info: AK68512D1C 524,288 x 8 Bit CMOS Static Random Access Memory ACCUTEK MICROCIRCUIT CORPORATION DESCRIPTION The Accutek AK68512D1C high density memory module is a static random access memory organized in 512K x 8 bit words. The assembly consists of one medium speed 512K x 8 SRAM in a TSOP

AK68512D1C

Contextual Info: AK68512D 524,288 x 8 Bit CMOS Static Random Access Memory ACCUTEK MICROCIRCUIT CORPORATION DESCRIPTION The Accutek AK68512D-1C high density memory module is a static random access memory organized in 512K x 8 bit words. The assembly consists of one medium speed 512K x 8 SRAM in a TSOP

89C1632

Contextual Info: 89C1632 16 Megabit 512K x 32-Bit MCM SRAM 16 Megabit (512k x 32-bit) SRAM MCM CS 1-4 Address OE, WE Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM I/O 8-15 I/O 16-23 I/O 24-31 Ground MCM Memory I/O 0-7 Logic Diagram FEATURES: DESCRIPTION: • Four 512k x 8 SRAM architecture

89C1632

Abstract: 512K x 8 bit sram 32 pin
Contextual Info: 89C1632 16 Megabit 512K x 32-Bit MCM SRAM 16 Megabit (512k x 32-bit) SRAM MCM CS 1-4 Address OE, WE Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM I/O 8-15 I/O 16-23 I/O 24-31 Ground MCM Memory I/O 0-7 Logic Diagram FEATURES: DESCRIPTION: • Four 512k x 8 SRAM architecture

A61L9308S-10

Abstract: A61L9308S-12 A61L9308S-8 A61L9308V-8
Contextual Info: A61L9308 Series Preliminary 512K X 8 BIT HIGH SPEED CMOS SRAM Document Title 512K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue October 22, 1999 Preliminary October, 1999, Version 0.0 AMIC Technology, Inc.

Contextual Info: LP62S4096F-T Series Preliminary 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue June 6, 2006 Preliminary June, 2006, Version 0.0 AMIC Technology, Corp.

TVR diode

Abstract: 0-00C4
Contextual Info: LP61L4096-I Series 512K X 8 BIT 3V HIGH SPEED CMOS SRAM Preliminary Document Title 512K X 8 BIT 3V HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue January 6, 2009 Preliminary January, 2009, Version 0.0

89C1632

Abstract: SRAM 6264 6264 SRAM
Contextual Info: 89C1632 16 Megabit 512K x 32-Bit MCM SRAM 16 Megabit (512k x 32-bit) SRAM MCM CS 1-4 Address OE, WE Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM I/O 8-15 I/O 16-23 I/O 24-31 Ground MCM Memory I/O 0-7 Logic Diagram FEATURES: DESCRIPTION: • Four 512k x 8 SRAM architecture

Contextual Info: LP614096-I Series 512K X 8 BIT 5V HIGH SPEED CMOS SRAM Preliminary Document Title 512K X 8 BIT 5V HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue January 7, 2009 Preliminary January, 2009, Version 0.0

Contextual Info: LP62S4096F-I Series Preliminary 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue June 6, 2006 Preliminary June, 2006, Version 0.0 AMIC Technology, Corp.

bd 9897 fs

Abstract: btm 220 btm 330 ha 1555 btm 110 ST2104 W65C02S ST2-10
Contextual Info: ST Sitronix ST2104 8 BIT Microcontroller with 512K bytes ROM PRELIMINARY Notice: This is not a final specification. Some parameters are subject to change. 1. FEATURES Totally static 65C02S CPU ROM: 512K x 8-bit RAM: 4K x 8-bit Stack: Up to 128-level deep Operation voltage:

LP62S4096E-T

Abstract: LP62S4096EV-55LLT LP62S4096EX-55LLT
Contextual Info: LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification

LP62S4096EX-70LLTF

Abstract: tvr 1024 LP62S4096E-T LP62S4096EU-55LLT LP62S4096EU-55LLTF LP62S4096EX-55LLTF
Contextual Info: LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification

as6c4008-55PCN

Abstract: as6c4008-55sin as6c4008-55 AS6C4008 as6c4008-55p 55pcn
Contextual Info: OCTOBER January 20072007 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply

LP62S4096EV-70LLTF

Abstract: LP62S4096E-T LP62S4096EV-55LLT LP62S4096EV-55LLTF LP62S4096EX-70LLTF lp62s4096eu-70lltf
Contextual Info: LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification

LP62S4096E-I

Abstract: LP62S4096EV-55LLI
Contextual Info: LP62S4096E-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification

Contextual Info: LP62S4096F-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History History Issue Date 0.0 Initial issue June 6, 2006 Preliminary 1.0 Final version release March 6, 2007 Final Rev. No. March, 2007, Version 1.0

LP62S4096E-I

Abstract: LP62S4096EU-55LLI
Contextual Info: LP62S4096E-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification

AS6C4008-55PCN

Abstract: AS6C4008 AS6C4008-55SIN AS6C4008-55TIN AS6C4008-55
Contextual Info: January 20072007 February AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply

LP62S4096E-I

Abstract: LP62S4096EV-55LLI LP62S4096EX-55LLI
Contextual Info: LP62S4096E-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification

Contextual Info: January 2007 February 2007 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply