54S260 Search Results

diagram CD 5265 cs

Contextual Info: TYPES 54S260, SN74S260 DUAL 5-INPUT POSITIVE -NOR GATES REVISED DECEM BER 1983 SN 54S260 I OR W PACKAGE SN 74S260 . . . D, J OR N PACKAGE Package Options Include Both Plastic and Ceram ic Chip Carriers in Addition to Plastic and Ceram ic DIPs {TOP VIEW

Contextual Info: 260 CONNECTION DIAGRAM PINOUT A 54S/74S260 6>/0^c+o i/54LS/74LS260 O H ö q q DUAL 5-INPUT NOR GATE E ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%. T a = 0° C to +70° C V cc = + 5 .0 V ±10%, T a = -55° C to +125° C

54S38

Abstract: SN74298 SN74265 54175 NES 1004 naval specification 74L95 Transistor AF 138 07802-1 SN7437 SN54LS195A
Contextual Info: m - G EN ER A L IN F O R M A TIO N INDEXES Numerical • Functional/Selection Guide O R D E R IN G INSTRUCTIO NS A N D M E C H A N IC A L D ATA 1 1 5 4/74 F A M IL Y SSI C IR CU ITS 2 I 54/74 F A M IL Y M S I/LSI C IR C U ITS 3 S E R IE S 29000 S S I C IR C U IT S

2650B

Abstract: wf vqc 10d alu 9308 d Signetics 2650 SN52723 2650 cpu 82S103 pipbug Signetics NE561 cd 75232
Contextual Info: flcnCTICf ßii>ouiR/mos fflICROPROCEÍSOR DATfl mnnuni SIGNETICS reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Signetics also assumes no responsibility for the

Contextual Info: 54S260, SN74S260 DUAL 5-INPUT POSITIVE-NOR GATES DECEMBER 1 9 8 3 - REVISED M AR C H 1 9 8 8 SN5 4 8 2 6 0 . . . J OR W PACKAGE SN 74S 260 . . . D OR N PACKAGE • Package Options Include Ceramic Chip Carriers and Flat Packages in Addition to Plastic and Ceramic DIPs

74LS260PC

Abstract: 54LS260DM 54S260DM 54S260FM 74LS260DC 74LS260FC 74S260DC 74S260FC 74S260PC 74s260
Contextual Info: 260 CONNECTION DIAGRAM PINOUT A 54S/74S260 ^ 4 L S /7 4 L S 2 6 0 e?/ O !/ 6 <5 DUAL 5-IN P U T NOR GATE ORDERING CODE: See Section S PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%. Ta = 0 °C to +70° C V cc = +5.0 V ±10%, T a — -55° C to + 125°C

74S00 TTL

Abstract: 54S112 54s350 54S35
Contextual Info: SCHOTTKYTTL 1» SIGNETICS INTEGRATED CIRCUITS 54S00 Series 74S00 Series The 54S00/74S00 series of product is fabricated with a non­ s a tu ra tin g S c h o ttk y cla m p e d transistor technique. This family of TTL product consists of very high performance and high power

logos 4012B

Abstract: 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485
Contextual Info: L p i > « , * S E m Ic O N VOLUM E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 5th EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY S E M IC O N IN D E X E S L IM IT E D THE SEMICON INDEX SERIES CONSISTS OF VOLUME 1 TRANSISTOR INDEX VOLUME 2 DIODE & SCR INDEX

Contextual Info: I NATIONAL SEMICOND { L O G I C } OSE D I bSDHE2 □□t>3c17S b I 260 260 C O N N EC T IO N DIA G RAM PIN O U T A 54S/74S260 54LS/74LS260 DU AL 5-INPUT N O R G A T E O RD ER IN G CODE: See Section 9 PIN PK G S C O M M E R C IA L GRAD E MILITARY GRAD E Vcc = +5.0 V ±5%,