558 DIVIDER BUFFERS Search Results

Contextual Info: UM10314 LPC3130/31 User manual Rev. 2 — 23 May 2012 Document information Info Content Keywords LPC3130, LPC3131, ARM9, USB Abstract LPC3130/31 User manual User manual UM10314 NXP Semiconductors LPC3130/31 User manual Revision history Rev Date Description

Contextual Info: LOGIC DEVICES INC 5 aE D • SSbS^QS 0001211 4 ■ _ T - 9 3 -07 LMU557/558 8 x 8-bit Parallel Multiplier ! DESCRIPTION FEATURES The LMU557 and LMU558 are 8-bit parallel multipliers with high speed and low power operation. They are

Contextual Info: LMU557/558 8 x 8-bit Parallel Multiplier Features_ Description_ □ 60 ns worst-case multiply time The LMU557 and LMU558 are 8-bit parallel multipliers with high speed and low power operation. They are pin for pin equivalents with 54S557

"Pin for Pin"

Abstract: LMU557 B-739 LMU558DC U-558D
Contextual Info: LMU557/558 8 x 8-bit Parallel Multiplier Features Description □ 60 ns worst-case multiply time The LMU557 and LMU558 are 8-bit parallel multipliers with high speed and low power operation. They are pin for pin equivalents with 54S557 and 54S558 type multipliers. Full

block diagram 8x8 booth multiplier

Abstract: 25S558 comparison between intel 8086 and Zilog 80 microprocessor mPD7720 intel 8087 74S508 74S556 8x8 booth multiplier 67558-1 25S557
Contextual Info: Five New Ways to Go Forth and Multiply Chuck Hastings Our Multiplier Population Explosion Recently it has seemed as if every time you turned around Monolithic Memories was announcing another new multiplier. Want to catch your breath, and find out where each of these fits

74AC154

Abstract: design octal counter using j-k flipflop HD74HC04 octal counter application octal decoder ic HD74HC259 HD74HC126 HD74HC373
Contextual Info: Contents I General Information. HD74AC Scries. y 9 FA C T Descriptions and Fam ily Characteristics . n Defenition o f Specifications. 20 Design Considerations. 29 •HD74HC Series.

1010 817 D21 B

Abstract: M68MEVB1632 A-18 D-20 ICD16 SPWM 555 DSA0039272 D44 connector 922 motorola stepper drive D28
Contextual Info: INDEX –A– data word 4-26 I/O block diagram 4-25 interface 4-24 peripheral interface protocol SPI 4-25 sources 4-20 debugging mode freeze assertion diagram A-18 serial communication diagram A-18 timing A-18 Base ID mask bits D-90 Basic operand size 5-24

D73 -Y

Abstract: M68MEVB1632 IC 555 timer motor control 1010 817 D21 B transmitter module spwm tx - 4 A-18 D-20 555 stepper pulse generator d11 1117 d92 02
Contextual Info: Freescale Semiconductor, Inc. INDEX Freescale Semiconductor, Inc. –A– data word 4-26 I/O block diagram 4-25 interface 4-24 peripheral interface protocol SPI 4-25 sources 4-20 debugging mode freeze assertion diagram A-18 serial communication diagram A-18

27256 ROM

Contextual Info: HD64530— LAPD Controller Description The HD64530 one-chip CMOS communica­ tions device supports the LAPD protocol and conforms to the ISDN integrated ser­ vices digital network standard. LAPD is layer 2 of the international ISDN standard specified by ITU-T recommendations 1.440

IS07816

Contextual Info: Features • • • • • • • • • • • • • Compatible with an Embedded ARM7TDMI Processor Programmable Baud Rate Generator Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes

Contextual Info: Features • • • • • • • • • • • • • Compatible with an Embedded ARM7TDMI Processor Programmable Baud Rate Generator Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes

Contextual Info: Features • • • • • • • • • • • • • • Compatible with an Embedded ARM7TDMI Processor Programmable Baud Rate Generator Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes

circuit diagram video transmitter and receiver

Abstract: video transmitter 2.4 GHz EP2AGX65DF29 circuit diagram of rf transmitter and receiver EP2AGX95EF29 CPRI CDR EP2AGX190EF29 remote control transmitter and receiver circuit 5 channel RF transmitter and Receiver circuit active noise cancellation for FPGA
Contextual Info: Section I. Transceiver Architecture This section provides information about Arria II GX transceiver architecture and clocking. It also describes configuring multiple protocols, data rates, and reset control and power down in the Arria II GX device family. This section includes the following

SP8855E

Contextual Info: SP8855E 2.8GHz Parallel Load Professional Synthesiser Advance Information DS4239 The SP8855E is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a PLL synthesis loop. Other devices in the series are the SP8852E which is a fully programmable

GPON block diagram

Abstract: hd-SDI deserializer LVDS SDI SERIALIZER EP2AGX95EF29 EP2AGX190EF29 SerialLite EP2AGX190 ep2agx65df ENCODER 8 BITS d2151
Contextual Info: 1. Arria II GX Transceiver Architecture AIIGX52001-3.0 This chapter describes all the modules that are available in the Arria II GX transceiver architecture and describes how these modules are used in the protocols shown below. In addition, this chapter lists the available test modes, dynamic

AD9553

Abstract: GR-253 GR-253-CORE JESD51-2 MO-220-WHHD NF75
Contextual Info: Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet AD9553 FEATURES GENERAL DESCRIPTION Input frequencies from 8 kHz to 710 MHz Output frequencies up to 810 MHz Preset pin-programmable frequency translation ratios cover popular wireline and wireless frequency applications,

USART2

Abstract: ISO7816
Contextual Info: Features • • • • • • • • • • • • • Compatible with an Embedded ARM7TDMI Processor Programmable Baud Rate Generator Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes

PROTOCOL RS485 WITH ATMEL

Abstract: ISO7816 IS0-7816
Contextual Info: Features • • • • • • • • • • • • • • Compatible with an Embedded ARM7TDMI Processor Programmable Baud Rate Generator Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes

TDC1009

Abstract: TDC-1009 trw 2009
Contextual Info: LOGIC DEVICES INC 2bE D SSbSTQS OGOiaSÌ s T - 9 S -Ô 7 12 x 12-bit Multiplier-Accumuiator FEATURES LM A 10 0 9 /2 0 0 9 D E S C R IP T IO N □ 45 ns Worst-Case M ultiplyAccumulate Time The LMA1009 and LMA2009 are 12-bit CMOS multiplier-accumulators. They are pm-for-pirt equivalent to the

AD9289

Abstract: AD9289BBC-65 AD9289BBC-65EB ANSI644 ANSI-644
Contextual Info: Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter AD9289 Preliminary Technical Data FEATURES FUNCTIONAL BLOCK DIAGRAM • Four ADCs in one package DRGND AVDD • Serial LVDS digital output data rates up to 520 Mbps ANSI644 PDWN DRVDD OR+ OR- S1 AD9289 • Data clock output provided

circuit diagram of motherboard laptop nec reset section

Abstract: NEC 765A WD7600 cmo 765 EM- 546 stepper motor laptop HARD DISK CIRCUIT diagram floppy disk Stepper Motors 80387SX MC146818A WD76C20LV
Contextual Info: WD76C20lLV TABLE OF CONTENTS Page Section Title 1.0 INTRODUCTION 1.1 Document Scope 1.2 Features 1.3 General Description 5-1 5-1 5-1 5-3 2.0 ARCHITECTURE 2.1 Bus Interface Logic 2.2 Chip Select Logic . 2.3 Floppy Disk Controller 2.4 Real Time Clock and SRAM

LM1208

Abstract: crt monitor block diagram differential pair cascode differential pair cascode darlington THR9 TRANSISTOR C 6090 LM1208N
Contextual Info: January 1994 LM1208 130 MHz RGB Video Amplifier System with Blanking General Description The LM 1208 is a very high frequency video amplifier system intended for use in high resolution RGB monitor applica­ tions. In addition to the three matched video amplifiers, the

EZ 742

Abstract: ST EZ 725 W156CH 24MHZ 48MHZ W156C eZ 752 sk 4012 cypress COUNTRY OF ORIGIN CRYSTAL14
Contextual Info: PRELIMINARY • / CYPRESS W156C Spread Spectrum FTG for VIA MVP4 Features Table 1. M ode In p u t Table • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Single-chip implementation • Four copies of CPU output • Six copies of PCI output

Contextual Info: TSC2117 www.ti.com SLAS550B – APRIL 2009 – REVISED JUNE 2012 Low-Power Audio Codec with Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller Check for Samples: TSC2117 1 INTRODUCTION 1.1 Features • Low-Power 13-mW Stereo 48-kHz Playback