625MH Search Results

MAX4304

Abstract: 052E-11 SOT23-8 VA7 MAX4104 MAX4105 MAX4305 D-Sub 50
Contextual Info: * MAX4104 FAMILY MACROMODELS * -* FEATURES: * 625MHz Bandwidth MAX4104 * 730MHz Bandwidth (MAX4304) * 410MHz Bandwidth (MAX4105) * 340MHz Bandwidth (MAX4305) * * Low-Noise and Low-Distortion * 100MHz 0.1dB Gain Flatness * * Available in 5-Pin SOT23

Ctr32

Contextual Info: RF5604 RF56045 V, 475MHz to 625MHz FEM 5V, 475MHZ TO 625MHZ FEM Package: 20-Pin, 4.5mmx4.5mmx0.975mm        Vdd 20 19 18 17 GND 2 15 C_PD GND 3 14 GND GND 4 13 5 12 GND 11 GND TX_IN Applications C_ATT 16 RX_OUT Integrated 50 Input/Output

Contextual Info: Crystal-to-LVPECL/LVDS Clock Synthesizer ICS849S625I DATA SHEET General Description Features The ICS849S625I is a high frequency clock generator. The ICS849S625I uses an external 25MHz crystal to synthesize 625MHz, 312.5MHz, 156.25MHz and 125MHz clocks. The

Contextual Info: Rev 0; 3/09 3.3V Dual-Output LVPECL Clock Oscillator The DS4625 is a dual-output, low-jitter clock oscillator capable of producing frequency output pair combinations ranging from 100MHz to 625MHz. The device combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop PLL in a 5.0mm x 3.2mm

Contextual Info: RF5604 RF56045 V, 475MHz to 625MHz FEM 5V, 475MHZ TO 625MHZ FEM Package: 20-Pin, 4.5mmx4.5mmx0.975mm        Vdd 20 19 18 17 GND 2 15 C_PD GND 3 14 GND GND 4 13 5 12 GND 11 GND TX_IN Applications C_ATT 16 RX_OUT Integrated 50 Input/Output

ic 4558 pin diagram

Abstract: ic 4558 4558 4558 PIN 4558 pin configuration f 4558 fc 4558 IC 4558 CIRCUIT DIAGRAM JESD97 L1053
Contextual Info: 19-4558; Rev 0; 4/09 3.3V Dual-Output LVPECL Clock Oscillator The DS4625 is a dual-output, low-jitter clock oscillator capable of producing frequency output pair combinations ranging from 100MHz to 625MHz. The device combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop PLL in a 5.0mm x 3.2mm

ICS49

Abstract: 849S625BYILFT ICS49S625BIL ICS849S625I
Contextual Info: Crystal-to-LVPECL/LVDS Clock Synthesizer ICS849S625I DATA SHEET General Description Features The ICS849S625I is a high frequency clock generator. The ICS849S625I uses an external 25MHz crystal to synthesize 625MHz, 312.5MHz, 156.25MHz and 125MHz clocks. The

gn1405

Abstract: 484-pin BGA 10GHzVCO ASIC R2
Contextual Info: GN1405C Quad 5Gb/s SerDes with Equalizer GN1405C Product Brief Features Description • multi-rate serial operation: 1.25Gb/s, 2.5Gb/s, or 5Gb/s per channel • low output jitter • 1.25Gb/s Source Synchronous LVDS parallel interface • 625MHz DDR clocking on source synchronous

JESD97

Abstract: L1053
Contextual Info: 19-4558; Rev 1; 3/10 3.3V Dual-Output LVPECL Clock Oscillator The DS4625 is a dual-output, low-jitter clock oscillator capable of producing frequency output pair combinations ranging from 100MHz to 625MHz. The device combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop PLL in a 5.0mm x 3.2mm

Contextual Info: 19-4558; Rev 1; 3/10 3.3V Dual-Output LVPECL Clock Oscillator The DS4625 is a dual-output, low-jitter clock oscillator capable of producing frequency output pair combinations ranging from 100MHz to 625MHz. The device combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop PLL in a 5.0mm x 3.2mm

Contextual Info: TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com TMS320C6472 Fixed-Point Digital Signal Processor 1 Features • • • • • • • • • • • Congestion Control • IEEE 1149.6 Compliant I/Os – UTOPIA • UTOPIA Level 2 Slave ATM Controller

CDCM61002RHBR

Contextual Info: CDCM61002 www.ti.com. SCAS870 – FEBRUARY 2009 Two Output, Integrated VCO, Low-Jitter Clock Generator

Contextual Info: CDCM61002 www.ti.com SCAS870C – FEBRUARY 2009 – REVISED FEBRUARY 2010 Two Output, Integrated VCO, Low-Jitter Clock Generator Check for Samples: CDCM61002 FEATURES 1 • 2 • • • • • • • • • • • One Crystal Reference Input Including 24.8832

Contextual Info: ICS810252DI-02 VCXO Jitter Attenuator & FemtoClock Multiplier NRND DATA SHEET General Description Features The ICS810252DI-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency

SY10E016

Abstract: MC10H016 SY100E016
Contextual Info: 8-BIT SYNCHRONOUS BINARY UP COUNTER SY10E016 SY100E016 DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ The SY10/100E016 are high-speed synchronous, presettable and cascadable 8-bit binary counters designed for use in new, high-performance ECL systems. Architecture

EV10AQ190AVTPY

Abstract: EV10AQ190 EV10AQ190A EV10AQ190AVTP EV10AQ190ACTPY dioda a4N
Contextual Info: EV10AQ190A Low power QUAD 10-bit 1.25 Gsps ADC Operating up to 5 Gsps Datasheet Main Features • Quad ADC with 10-bit Resolution Using e2v Proprietary Analog • • • • • • • • • • Input Cross-point Switch – 1.25 Gsps Sampling Rate in Four-channel Mode

Contextual Info: PI6LC48P0301 3-Output LVPECL Networking Clock Generator Features Description ÎÎThree The PI6LC48P0301 is a 3-output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions. Using a 19.53125MHz or 25MHz crystal, the most popular

Contextual Info: PI2PCIE2212 PCI Express 2.0, 1-Lane, 2:1 Mux/DeMux Switch w/ Single Enable Features Description • • • • • • • • • Pericom Semiconductor’s PI2PCIE2212 is a 4 to 2 differential, bi-directional channel multiplexer/demultiplexer switch. Due to

Ericsson TSR 491 628

Abstract: NT 1307c ericsson TSR 491 641 Ericsson nokia 1600 schematic diagram schematic diagram UPS active power 600 schematic diagram UPS 600 Power free marking code H02 schematic diagram UPS active power 400 tsi620-10gclv
Contextual Info: Tsi620 RapidIO Switch / RapidIO-to-PCI Bridge User Manual Preliminary October 2007 80D7000_MA001_02 Titlepage Trademarks TUNDRA is a registered trademark of Tundra Semiconductor Corporation Canada, U.S., and U.K. . TUNDRA, the Tundra logo, Tsi620, and Silicon Behind the Network, are trademarks of Tundra Semiconductor Corporation.

SY10E016

Contextual Info: SY10E016 SY100E016 FINAL 8-BIT SYNCHRONOUS BINARY UP COUNTER DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ The SY10/100E016 are high-speed synchronous, presettable and cascadable 8-bit binary counters designed for use in new, high-performance ECL systems. Architecture

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

texas handbook

Abstract: 1008-B
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.

cd 1619 CP

Abstract: RX SOP 1738 bc 494 b f.m transmitter Schematics AL 1450 DV hp 2212 sdc 2025 AL 2450 dv circuit diagram toggle switches 2041 BY TRANSISTOR BC 187 vhdl code for 16 prbs generator
Contextual Info: Stratix II GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIIGX5V1-4.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

crpa

Abstract: HD-SDI over sdh SSTL-15 HIV54001-1 SSTL-18 HC4GX35FF1517N M144K
Contextual Info: HardCopy IV Device Handbook, Volume 4 101 Innovation Drive San Jose, CA 95134 www.altera.com HC4_H5V4-1.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other