64K*1 DRAM Search Results

am9064

Abstract: cvp 45 Am90C644
Contextual Info: Am90C644 64K X 4 CMOS DUAL-ARRAY MEMORY ADVANCE INFORMATION 64K x 4 organization High-speed access: tpAC - 1 00 ns Write-per-Bit mask allows separatewrite controls for each of the four DRAM input bits On-chip video shifter with up to 100Megapixel/sec. bandwidth

4264 dram

Contextual Info: MICRON T E C H N O L O G Y INC 55E D • blllS4'ì DDDSb?^ 153 ■ MRN PRELIMINARY W1T4C4264 883C 64K X 1 DRAM | W |! C R Q N MILITARY DRAM 64K X 1 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883, Class B

Contextual Info: MT4C1670/1 L 64K X 16 DRAM |U |IC =R O N 64K x 16 DRAM STATIC COLUMN MODE, LOW POWER, EXTENDED REFRESH FEATURES PIN ASSIGNMENT Top View • Industry standard x l6 pinouts, tim ing, functions and packages • High-perform ance, CM OS silicon-gate process

Contextual Info: ADAPTEC INC y •: MME D ■ B OElMMlb GQG203D & D A A C ¿ m $ L - i .j " .'T 'S L ^ k '5 Ç\C\ A IP -Æ 1 r 1 1O U I U U Single-Chip PC/AT Mass Storage Controller DATA BUFFER SRAM 64K MAX DRAM 64K MAX 8 MB/sec 3,5/2,5 INCH HARD DISK t AT BUS DATA SEPARATOR

A101

Abstract: CY7C1333F CY7C1333F-100AC
Contextual Info: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous

A101

Abstract: CY7C1333F CY7C1333F-100AC 20306
Contextual Info: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous

20306

Contextual Info: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous

Contextual Info: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous

4264 dram

Contextual Info: AUSTI N S E M I C O N D U C T O R INC bOE D I D O E l l ? G G G G 1 1 4 7Ü4 H A U S T K K tL IM IN A K Y MT4C4264 883C 64K X 1 DRAM |U|IC=RON MILITARY DRAM 64K X 1 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883, Class B

n6480

Abstract: 347I
Contextual Info: HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS IDT707288S/L Features * * * * * 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 16K x 16 banks * - 1 M egabit o f mem ory on chip * Fast asynchronous address-to-data access time: 15ns

20306

Contextual Info: CY7C1333F 2-Mb 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states.Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support

Contextual Info: CY7C1333H PRELIMINARY 2-Mbit 64K x 32 Flow-Through SRAM with NoBL Architecture Features • Low standby power Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states. The CY7C1333H is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support

Switching regulator, Pin 5, Clock

Contextual Info: CY7C1333H PRELIMINARY 2-Mbit 64K x 32 Flow-Through SRAM with NoBL Architecture Features • Low standby power Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states. The CY7C1333H is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support

Contextual Info: HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS IDT707288S/L F e a tu re s * * * * * 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 16K x 16 banks * - 1 M egabit o f mem ory on chip * Fast asynchronous address-to-data access time: 15ns

3771 8 pin ic

Abstract: 3771 ic 8 pin 8 pin ic 3771 3771 1A7A1 3771- IC
Contextual Info: LOW POWER 3V CMOS SRAM 1 MEG 64K x 16-BIT ADVANCE INFORMATION IDT71V016L Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • The ID T71V016L is a 1,048,576-bit very low-pow er Static RAM organized as 64K x 16. It is fabricated using ID T’s highreliability CMOS technology. This state-of-the-art technology,

3771

Abstract: 3771 ic 8 pin
Contextual Info: LOW POWER 3V CMOS SRAM 1 MEG 64K x 16-BIT ADVANCE INFORMATION IDT71V016L Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • The ID T71V016L is a 1,048,576-bit very low-pow er Static RAM organized as 64K x 16. It is fabricated using ID T’s highreliability CMOS technology. This state-of-the-art technology,

7481 memory ics

Abstract: oti-037
Contextual Info: OAK TECHNOLOGY INC. OTI-037 SYSTEM BLOCK DIAGRAM REFRESH SIR SIW SMR OTI-037 -RASO -CAS -W E -O E -IO W R -RAS -CAS -W E -O E BUS INTERFACE PLANEO 64K BYTE MD0-MD7 DATA ADDRESS I MDO-MD7 ASEL SA8-SA16 -RAS -CAS WE -O E PLANE 1 64K BYTE RAS -CAS -W E -O E PLANE 2

58AZ

Contextual Info: Am29368 Advanced Micro Devices 1 Megabit Dynamic Memory Controller/Driver DMC DISTINCTIVE CHARACTERISTICS Provides control for 16K, 64K, and 256K and 1-megabit dynamic RAMs Outputs directly drive up to 88 DRAMs. with a guaran­ teed worst-case limit on the undershoot

78D015

Contextual Info: MT4C1670/1 64K X 16 DRAM | V | IC = R O N DRAM 64K x 16DRAM STATIC COLUMN MODE FEATURES PIN ASSIGNMENT Top View • Ind u stry sta n d a rd x l 6 p in o u ts, tim ing , fu n ctio n s and p ackages • • • • • • H ig h -p erfo rm an ce, C M O S silico n -g a te p ro cess

AM29368

Abstract: CGX068
Contextual Info: Am29368 Advanced Micro Devices 1 Megabit Dynamic Memory Controller/Driver DMC DISTINCTIVE CHARACTERISTICS Provides control for 16K, 64K, and 256K and 1-megabit dynamic RAMs Outputs directly drive up to 8 8 DRAMs, with a guaran­ teed worst-case limit on the undershoot

6164 ram memory

Contextual Info: a Am29368 Advanced Micro Devices 1 Megabit Dynamic Memory Controller/Driver DMC DISTINCTIVE CHARACTERISTICS Provides control for 16K, 64K, and 256K and 1-megabit dynamic RAMs Outputs directly drive up to 8 8 DRAMs, with a guaran­ teed worst-case limit on the undershoot

Contextual Info: J MN1020019 / 0219 / 0419 / 0819 MN1020019 / 0219 / 0419 / 0819 1 Type 1 ROM x8-bit/x16-bit External / 1 6K / 32K / 64K (External Memory Expandable) 1 RAM (x8-bit/x16-bit) 3K / 1 K / 2K / 3K (External Memory Expandable) I Minimum Instruction Execution Time

Contextual Info: 8-Bit Dynamic-RAM Driver with Three-state Outputs SN54/74S700/-1 SN54/74S731/-1 SN54/74S730/-1 SN54/74S734/-1 Ordering Information Features/ Benefits: • Provides MOS voltage levels lo r 16K and 64K DRAMs PART NUMBER PKG TEMP ENABLE POLARITY POWER • Undershoot of low-going output is less than -0 .5 V

Contextual Info: LOW POWER 2V CMOS SRAM 1 MEG 64K x 16-BIT ADVANCE INFORMATION IDT71T016 I n te g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: DESCRIPTION: • 64K x 16 Organization • Wide Operating Voltage Range: 1.8 to 2.7V • Commercial (0° to 70°C) and Industrial (-40° to 85°C)