6S6303 Search Results

Contextual Info: SN74LVC16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS320 - NOVEMBER 1993 - REVISED MARCH 1994 Member of the Texas Instruments Wldebus Family DOG OR DL PACKAGE TOP VIEW EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process 10EA B L 1

Contextual Info: SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES _ SCLSQ76A - DE CE M B E R 1982 - REVISED JA NUARY 1996 • Package Options Include Plastic Small-Outllne D , Shrink Small-Outllne (DB), Thin Shrink Small-Outllne (PW), and Ceramic Flat (W) Packages, Ceramic Chip

3Y20

Contextual Info: SN75186 QUADRUPLE DRIVER/RECEIVER WITH LOOPBACK D3389. FEBRUARY 1990 FN PACKAGE Meets Standards RS-232-C, EIA-232-D, and CCITT V.28 TOP VIEW Four Independent Drivers and Receivers CM O Ü z S I—JI—] L J L J , A 3 2 1 1 LB ] 5 N < Loopback Mode Functionally Self-Tests

Contextual Info: I T SN74LVC841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS307A-MARCH 1 9 9 3 -REVISED JULY 1995 DB, DW, OR PW PACKAQE TOP VIEW • EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • Typical Volp (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25°C

TLG2201

Abstract: TLC2201 TLC2201A TLC2201ACD TLC2201ACP TLC2201B TLC2201BCP TLC2201CP TLC2201Y ScansUX30
Contextual Info: TLC2201, TLC2201A, TLC2201B, TLC2201Y Advanced LinCMOS LOW-NOISE PRECISION OPERATIONAL AMPLIFIERS SLOSQ21A - NOVEMBER 1988 - REVISED AUGUST 1994 Low Input Bias Current 1 pA at TA = 25°C Fully Specified for Both Single-Supply and Split-Supply Operation

Contextual Info: SN54HCT74, SN74HCT74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS169A - DECEMBER 1962 - REVISED JANUARY 1996 Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outllne D , Thin Shrink

Contextual Info: SN54HC645, SN74HC645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS _ SCLS304-JANUARY 1996 * True Logic f • • High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Package Options Include Plastic Small-Outline DW and Ceramic Flat

TLC271 equivalent

Abstract: Tlc2711 TLC271 HB F 2480 TIC27 TLC271C DT317
Contextual Info: TLC271, TLC271A, TLC271B LinCMOS PROGAMMABLE LOW-POWER OPERATIONAL AMPLIFIERS SI.OS090A - NOVEMBER 1987 - REVISED AUGUST 1994 D, JG, OR P PACKAGE CTOP VIEW Input Offset Voltage D r ift. . . Typically 0.1 |xV/Month, Including the First 30 Days Wide Range of Supply Voltages Over

tlc15431

Abstract: TLC1643C TLC15421
Contextual Info: TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS052C - MARCH 1 9 9 2 -REVISED MARCH 1995 10-Blt-Resolution A/D Converter DB, J, DW, OR N PACKAGE TOP VIEW

SN74LVC244A

Contextual Info: SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS I SCAS414C - NOVEMBER 1992 - REVISED JULY 199S DB, DW, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

Contextual Info: SN75ALS053 QUAD FUTUREBUS TRANSCEIVER D 3 0 7 7 , JA N U A R Y 1 9 8 8 - REVISED SEPTEM BER 1989 N PACKAGE High-Speed Quad Transceiver TOP VIEW Fully Compatible with IEEE Std 8 9 6 .1 —1987 Futurebus Requirements vccC D1C R1 C D2[ R2[ LO G IC G N D C Drives Load Impedances as Low as 10 0

7s36

Abstract: SN54ABTE16245 SN74ABTE16245 TL1723 VME64 u6303 M6303 7s36s
Contextual Info: SN54ABTE16245, SN74ABTE16245 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS226D - JULY 1993 - REVISED AUGUST 1994 SN54ABTE16245. . . WD PACKAGE SN74ABTE16245. . . DGQ OR DL PACKAGE TOP VIEW • Supports the VME64 ETL Specification

Contextual Info: SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121A - DECEMBER 1982 - REVISED JANUARY 1996 • • Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous In Count Modes Asynchronously Presettable With Load

SN76175

Abstract: SN7S173 texas instruments rs 485
Contextual Info: Û clbl724 D D Ô 2 b7 S S m j I I H ' T ' “7 b '- c S - 0 $ 1 ° SN7S173 QUADRUPLE DIFFERENTIAL LINE RECEIVER I TEXAS INSTR 4QE D ( L I N / I NT FC D 2600, OCTOBER 1980-RÉV1SED JULY 1990 D, J, OR N PACKAGE (TOP VIEW) Meets EIA Standards RS-422-A, RS-423-A,

Contextual Info: SN54AHC245, SN74AHC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS23QB- OCTOBER 1995 - REVISED MARCH 1996 Operating Range 2-V to 5.5-V Vqc EPIC"* Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17

bd 8161

Contextual Info: SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS301A - JANUARY 1993 - REVISED JULY 1995 DB, DW, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • Typical V q l p (Output Ground Bounce)

1A07

Abstract: ET-1 1A06 1A08 1A09 2A02 2A03 SN54FB1651 SN74FB1651
Contextual Info: SN54FB1651, SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVERS WITH BUFFERED CLOCK LINES SCBS177B- OCTOBER 1993- REVISED JULY 1994 B-Port Biasing Network Preconditions the Connector and PC Trace to the Backplane Transceiver Logic High-Level Voltage TTL-lnput Structures Incorporate Active

Contextual Info: TEXAS INSTR LOGIC 31E D Bl 6Tbl753 QQfifl^ST 2 Bi TII3 54AC11646, 74AC11646 OCTAL BUS TRANSCEIVERS AND REGISTERS o , WITH 3-STATE OUTPUTS \ • • • • — J / J " O ' C > TI0097— D2957, JU LY 1987— REVISED MARCH 1990 54AC 11646 . . . J T PACKAGE

TlC1540

Contextual Info: TLC1540C, TLC1541C 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS _ SLAS073A- DECEMBER 1985 - REVISED MARCH 1995 10-Bit Resolution A/D Converter Microprocessor Peripheral or Stand-Alone Operation On-Chip 12-Channel Analog Multiplexer

Contextual Info: SN54AHCT86, SN74AHCT86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS26QB - OCTOBER 199S - REVISED MARCH 1996 SN54AHCTB6 . . . J OR W PACKAGE SN74AHCT86. . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EP/C (Enhanced-Performance Implanted

Contextual Info: SN74ACT53861 4096 x 18 CLOCKED MULTIPLE-QUEUE MULTI-Q FIRST-IN, FIRST-OUT MEMORY WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FUGS SCAS443A-JUNE 1994- REVISED JULY 1995 4096 x 18 Total Memory Size Three Programmable-Depth FIFOs on One Device Memory Allocation of 256 x 18 Blocks

Contextual Info: SN74ALVC16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS261 - JANUARY 1993 - REVISED MARCH 1994 • Member of the Texas Instruments Wldebus'“ Family | DGG OR DL PACKAGE TOP VIEW • UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type

Contextual Info: SN74LVCH16240A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS566F - MARCH 1996 - REVISED JANUARY 1998 Member of the Texas Instruments Wldebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process Typical Volp (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

222Z

Abstract: A20C A23C A28C SN74ACT3622 SN74ACT3632 SN74ACT3642 7526A S563
Contextual Info: SN74ACT3632 512 x 36 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SC AS224B - JUNE 1992 - REVISED SEPTEMBER 1994 IRB, ORB, AEB, and AFB Flags Synchronized by CLKB Low-Power 0.8-Mlcron Advanced CMOS Technology Supports Clock Frequencies up to 67 MHz Free-Running CLKA and CLKB Can Be